| Message ID | 20221020103120.1541862-4-dmitry.baryshkov@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | PCI: qcom: use clk_bulk API | expand |
On Thu, Oct 20, 2022 Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote: > > Change hand-coded implementation of bulk clocks to use the existing > clk_bulk_* API. > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > drivers/pci/controller/dwc/pcie-qcom.c | 68 ++++++-------------------- > 1 file changed, 15 insertions(+), 53 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c > index 74588438db07..eee4d2179e90 100644 > --- a/drivers/pci/controller/dwc/pcie-qcom.c > +++ b/drivers/pci/controller/dwc/pcie-qcom.c > @@ -139,11 +139,9 @@ struct qcom_pcie_resources_1_0_0 { > }; > > #define QCOM_PCIE_2_3_2_MAX_SUPPLY 2 > +#define QCOM_PCIE_2_3_2_MAX_CLOCKS 4 > struct qcom_pcie_resources_2_3_2 { > - struct clk *aux_clk; > - struct clk *master_clk; > - struct clk *slave_clk; > - struct clk *cfg_clk; > + struct clk_bulk_data clks[QCOM_PCIE_2_3_2_MAX_CLOCKS]; > struct regulator_bulk_data supplies[QCOM_PCIE_2_3_2_MAX_SUPPLY]; > }; > > @@ -571,21 +569,14 @@ static int qcom_pcie_get_resources_2_3_2(struct qcom_pcie *pcie) > if (ret) > return ret; > > - res->aux_clk = devm_clk_get(dev, "aux"); > - if (IS_ERR(res->aux_clk)) > - return PTR_ERR(res->aux_clk); > - > - res->cfg_clk = devm_clk_get(dev, "cfg"); > - if (IS_ERR(res->cfg_clk)) > - return PTR_ERR(res->cfg_clk); > - > - res->master_clk = devm_clk_get(dev, "bus_master"); > - if (IS_ERR(res->master_clk)) > - return PTR_ERR(res->master_clk); > + res->clks[0].id = "aux"; > + res->clks[1].id = "cfg"; > + res->clks[2].id = "master"; Hi Dmitry, I just have a simple question on clock names. The original clock name is 'bus_master', while your patch uses just 'master' as the clock name. As far as I know, the clock names are defined by clock side, not device driver side. Is it intentional? If so, would you please explain why it is ok? > + res->clks[3].id = "slave"; Ditto. Thank you. Best regards, Jingoo Han > > - res->slave_clk = devm_clk_get(dev, "bus_slave"); > - if (IS_ERR(res->slave_clk)) > - return PTR_ERR(res->slave_clk); > + ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks); > + if (ret < 0) > + return ret; > > return 0; > } > @@ -594,11 +585,7 @@ static void qcom_pcie_deinit_2_3_2(struct qcom_pcie *pcie) > { > struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2; > > - clk_disable_unprepare(res->slave_clk); > - clk_disable_unprepare(res->master_clk); > - clk_disable_unprepare(res->cfg_clk); > - clk_disable_unprepare(res->aux_clk); > - > + clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); > regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); > } > > @@ -615,40 +602,15 @@ static int qcom_pcie_init_2_3_2(struct qcom_pcie *pcie) > return ret; > } > > - ret = clk_prepare_enable(res->aux_clk); > - if (ret) { > - dev_err(dev, "cannot prepare/enable aux clock\n"); > - goto err_aux_clk; > - } > - > - ret = clk_prepare_enable(res->cfg_clk); > - if (ret) { > - dev_err(dev, "cannot prepare/enable cfg clock\n"); > - goto err_cfg_clk; > - } > - > - ret = clk_prepare_enable(res->master_clk); > - if (ret) { > - dev_err(dev, "cannot prepare/enable master clock\n"); > - goto err_master_clk; > - } > - > - ret = clk_prepare_enable(res->slave_clk); > - if (ret) { > - dev_err(dev, "cannot prepare/enable slave clock\n"); > - goto err_slave_clk; > + ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks); > + if (ret < 0) { > + dev_err(dev, "cannot prepare/enable clocks\n"); > + goto err_clks; > } > > return 0; > > -err_slave_clk: > - clk_disable_unprepare(res->master_clk); > -err_master_clk: > - clk_disable_unprepare(res->cfg_clk); > -err_cfg_clk: > - clk_disable_unprepare(res->aux_clk); > - > -err_aux_clk: > +err_clks: > regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); > > return ret; > -- > 2.35.1 >
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 74588438db07..eee4d2179e90 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -139,11 +139,9 @@ struct qcom_pcie_resources_1_0_0 { }; #define QCOM_PCIE_2_3_2_MAX_SUPPLY 2 +#define QCOM_PCIE_2_3_2_MAX_CLOCKS 4 struct qcom_pcie_resources_2_3_2 { - struct clk *aux_clk; - struct clk *master_clk; - struct clk *slave_clk; - struct clk *cfg_clk; + struct clk_bulk_data clks[QCOM_PCIE_2_3_2_MAX_CLOCKS]; struct regulator_bulk_data supplies[QCOM_PCIE_2_3_2_MAX_SUPPLY]; }; @@ -571,21 +569,14 @@ static int qcom_pcie_get_resources_2_3_2(struct qcom_pcie *pcie) if (ret) return ret; - res->aux_clk = devm_clk_get(dev, "aux"); - if (IS_ERR(res->aux_clk)) - return PTR_ERR(res->aux_clk); - - res->cfg_clk = devm_clk_get(dev, "cfg"); - if (IS_ERR(res->cfg_clk)) - return PTR_ERR(res->cfg_clk); - - res->master_clk = devm_clk_get(dev, "bus_master"); - if (IS_ERR(res->master_clk)) - return PTR_ERR(res->master_clk); + res->clks[0].id = "aux"; + res->clks[1].id = "cfg"; + res->clks[2].id = "master"; + res->clks[3].id = "slave"; - res->slave_clk = devm_clk_get(dev, "bus_slave"); - if (IS_ERR(res->slave_clk)) - return PTR_ERR(res->slave_clk); + ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks); + if (ret < 0) + return ret; return 0; } @@ -594,11 +585,7 @@ static void qcom_pcie_deinit_2_3_2(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2; - clk_disable_unprepare(res->slave_clk); - clk_disable_unprepare(res->master_clk); - clk_disable_unprepare(res->cfg_clk); - clk_disable_unprepare(res->aux_clk); - + clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); } @@ -615,40 +602,15 @@ static int qcom_pcie_init_2_3_2(struct qcom_pcie *pcie) return ret; } - ret = clk_prepare_enable(res->aux_clk); - if (ret) { - dev_err(dev, "cannot prepare/enable aux clock\n"); - goto err_aux_clk; - } - - ret = clk_prepare_enable(res->cfg_clk); - if (ret) { - dev_err(dev, "cannot prepare/enable cfg clock\n"); - goto err_cfg_clk; - } - - ret = clk_prepare_enable(res->master_clk); - if (ret) { - dev_err(dev, "cannot prepare/enable master clock\n"); - goto err_master_clk; - } - - ret = clk_prepare_enable(res->slave_clk); - if (ret) { - dev_err(dev, "cannot prepare/enable slave clock\n"); - goto err_slave_clk; + ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks); + if (ret < 0) { + dev_err(dev, "cannot prepare/enable clocks\n"); + goto err_clks; } return 0; -err_slave_clk: - clk_disable_unprepare(res->master_clk); -err_master_clk: - clk_disable_unprepare(res->cfg_clk); -err_cfg_clk: - clk_disable_unprepare(res->aux_clk); - -err_aux_clk: +err_clks: regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); return ret;
Change hand-coded implementation of bulk clocks to use the existing clk_bulk_* API. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/pci/controller/dwc/pcie-qcom.c | 68 ++++++-------------------- 1 file changed, 15 insertions(+), 53 deletions(-)