| Message ID | 20220704152746.807550-6-dmitry.baryshkov@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | PCI: dwc: Fix higher MSI vectors handling | expand |
On Mon, Jul 04, 2022 at 06:27:45PM +0300, Dmitry Baryshkov wrote: > On Qualcomm platforms each group of 32 MSI vectors is routed to the > separate GIC interrupt. Document mapping of additional interrupts. > > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > Reviewed-by: Rob Herring <robh@kernel.org> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > .../devicetree/bindings/pci/qcom,pcie.yaml | 51 +++++++++++++++++-- > 1 file changed, 48 insertions(+), 3 deletions(-) > > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > index c40ba753707c..ee5414522e3c 100644 > --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > @@ -43,11 +43,12 @@ properties: > maxItems: 5 > > interrupts: > - maxItems: 1 > + minItems: 1 > + maxItems: 8 > > interrupt-names: > - items: > - - const: msi > + minItems: 1 > + maxItems: 8 > > # Common definitions for clocks, clock-names and reset. > # Platform constraints are described later. > @@ -623,6 +624,50 @@ allOf: > - resets > - reset-names > > + # On newer chipsets support either 1 or 8 msi interrupts > + # On older chipsets it's always 1 msi interrupt > + - if: > + properties: > + compatibles: This still has the misspelled property name here (plural s) so the conditional is always false. I know I included a fix for this in my follow-on series, but if you are respinning the series anyway you should fix it up. > + contains: > + enum: > + - qcom,pcie-msm8996 > + - qcom,pcie-sc7280 > + - qcom,pcie-sc8180x > + - qcom,pcie-sdm845 > + - qcom,pcie-sm8150 > + - qcom,pcie-sm8250 > + - qcom,pcie-sm8450-pcie0 > + - qcom,pcie-sm8450-pcie1 > + then: > + oneOf: > + - properties: > + interrupts: > + maxItems: 1 > + interrupt-names: > + items: > + - const: msi > + - properties: > + interrupts: > + minItems: 8 > + interrupt-names: > + items: > + - const: msi0 > + - const: msi1 > + - const: msi2 > + - const: msi3 > + - const: msi4 > + - const: msi5 > + - const: msi6 > + - const: msi7 > + else: > + properties: > + interrupts: > + maxItems: 1 > + interrupt-names: > + items: > + - const: msi > + > unevaluatedProperties: false > > examples: Johan
On 07/07/2022 11:06, Johan Hovold wrote: > On Mon, Jul 04, 2022 at 06:27:45PM +0300, Dmitry Baryshkov wrote: >> On Qualcomm platforms each group of 32 MSI vectors is routed to the >> separate GIC interrupt. Document mapping of additional interrupts. >> >> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> >> Reviewed-by: Rob Herring <robh@kernel.org> >> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> >> --- >> .../devicetree/bindings/pci/qcom,pcie.yaml | 51 +++++++++++++++++-- >> 1 file changed, 48 insertions(+), 3 deletions(-) >> >> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml >> index c40ba753707c..ee5414522e3c 100644 >> --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml >> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml [...] >> @@ -623,6 +624,50 @@ allOf: >> - resets >> - reset-names >> >> + # On newer chipsets support either 1 or 8 msi interrupts >> + # On older chipsets it's always 1 msi interrupt >> + - if: >> + properties: >> + compatibles: > > This still has the misspelled property name here (plural s) so the > conditional is always false. > > I know I included a fix for this in my follow-on series, but if you are > respinning the series anyway you should fix it up. Done, thanks a lot pointing me to it. > >> + contains: >> + enum: >> + - qcom,pcie-msm8996 [...]
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index c40ba753707c..ee5414522e3c 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -43,11 +43,12 @@ properties: maxItems: 5 interrupts: - maxItems: 1 + minItems: 1 + maxItems: 8 interrupt-names: - items: - - const: msi + minItems: 1 + maxItems: 8 # Common definitions for clocks, clock-names and reset. # Platform constraints are described later. @@ -623,6 +624,50 @@ allOf: - resets - reset-names + # On newer chipsets support either 1 or 8 msi interrupts + # On older chipsets it's always 1 msi interrupt + - if: + properties: + compatibles: + contains: + enum: + - qcom,pcie-msm8996 + - qcom,pcie-sc7280 + - qcom,pcie-sc8180x + - qcom,pcie-sdm845 + - qcom,pcie-sm8150 + - qcom,pcie-sm8250 + - qcom,pcie-sm8450-pcie0 + - qcom,pcie-sm8450-pcie1 + then: + oneOf: + - properties: + interrupts: + maxItems: 1 + interrupt-names: + items: + - const: msi + - properties: + interrupts: + minItems: 8 + interrupt-names: + items: + - const: msi0 + - const: msi1 + - const: msi2 + - const: msi3 + - const: msi4 + - const: msi5 + - const: msi6 + - const: msi7 + else: + properties: + interrupts: + maxItems: 1 + interrupt-names: + items: + - const: msi + unevaluatedProperties: false examples: