| Message ID | 20220624041950.559155-6-dan.j.williams@intel.com |
|---|---|
| State | New |
| Headers | show |
| Series | CXL PMEM Region Provisioning | expand |
On Thu, 23 Jun 2022 21:19:35 -0700 Dan Williams <dan.j.williams@intel.com> wrote: > Unless and until accelerator (type-2) drivers start registering for > CXL.mem mapping services from the CXL subsystem core, initialize idle > HDM decoders to the "expander" type. I.e. the only CXL devices using the > CXL core presently are those implementing the CXL 2.0 Type-3 memory > expander device class code that the cxl_pci driver claims. > > Signed-off-by: Dan Williams <dan.j.williams@intel.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> > --- > drivers/cxl/core/hdm.c | 16 +++++++++++----- > 1 file changed, 11 insertions(+), 5 deletions(-) > > diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c > index 672bf3e97811..7b58f6911523 100644 > --- a/drivers/cxl/core/hdm.c > +++ b/drivers/cxl/core/hdm.c > @@ -474,6 +474,17 @@ static int init_hdm_decoder(struct cxl_port *port, struct cxl_decoder *cxld, > cxld->flags |= CXL_DECODER_F_ENABLE; > if (ctrl & CXL_HDM_DECODER0_CTRL_LOCK) > cxld->flags |= CXL_DECODER_F_LOCK; > + if (FIELD_GET(CXL_HDM_DECODER0_CTRL_TYPE, ctrl)) > + cxld->target_type = CXL_DECODER_EXPANDER; > + else > + cxld->target_type = CXL_DECODER_ACCELERATOR; > + } else { > + /* unless / until type-2 drivers arrive, assume type-3 */ > + if (FIELD_GET(CXL_HDM_DECODER0_CTRL_TYPE, ctrl) == 0) { > + ctrl |= CXL_HDM_DECODER0_CTRL_TYPE; > + writel(ctrl, hdm + CXL_HDM_DECODER0_CTRL_OFFSET(which)); > + } > + cxld->target_type = CXL_DECODER_EXPANDER; > } > rc = cxl_to_ways(FIELD_GET(CXL_HDM_DECODER0_CTRL_IW_MASK, ctrl), > &cxld->interleave_ways); > @@ -488,11 +499,6 @@ static int init_hdm_decoder(struct cxl_port *port, struct cxl_decoder *cxld, > if (rc) > return rc; > > - if (FIELD_GET(CXL_HDM_DECODER0_CTRL_TYPE, ctrl)) > - cxld->target_type = CXL_DECODER_EXPANDER; > - else > - cxld->target_type = CXL_DECODER_ACCELERATOR; > - > if (!cxled) { > target_list.value = > ioread64_hi_lo(hdm + CXL_HDM_DECODER0_TL_LOW(which));
diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c index 672bf3e97811..7b58f6911523 100644 --- a/drivers/cxl/core/hdm.c +++ b/drivers/cxl/core/hdm.c @@ -474,6 +474,17 @@ static int init_hdm_decoder(struct cxl_port *port, struct cxl_decoder *cxld, cxld->flags |= CXL_DECODER_F_ENABLE; if (ctrl & CXL_HDM_DECODER0_CTRL_LOCK) cxld->flags |= CXL_DECODER_F_LOCK; + if (FIELD_GET(CXL_HDM_DECODER0_CTRL_TYPE, ctrl)) + cxld->target_type = CXL_DECODER_EXPANDER; + else + cxld->target_type = CXL_DECODER_ACCELERATOR; + } else { + /* unless / until type-2 drivers arrive, assume type-3 */ + if (FIELD_GET(CXL_HDM_DECODER0_CTRL_TYPE, ctrl) == 0) { + ctrl |= CXL_HDM_DECODER0_CTRL_TYPE; + writel(ctrl, hdm + CXL_HDM_DECODER0_CTRL_OFFSET(which)); + } + cxld->target_type = CXL_DECODER_EXPANDER; } rc = cxl_to_ways(FIELD_GET(CXL_HDM_DECODER0_CTRL_IW_MASK, ctrl), &cxld->interleave_ways); @@ -488,11 +499,6 @@ static int init_hdm_decoder(struct cxl_port *port, struct cxl_decoder *cxld, if (rc) return rc; - if (FIELD_GET(CXL_HDM_DECODER0_CTRL_TYPE, ctrl)) - cxld->target_type = CXL_DECODER_EXPANDER; - else - cxld->target_type = CXL_DECODER_ACCELERATOR; - if (!cxled) { target_list.value = ioread64_hi_lo(hdm + CXL_HDM_DECODER0_TL_LOW(which));
Unless and until accelerator (type-2) drivers start registering for CXL.mem mapping services from the CXL subsystem core, initialize idle HDM decoders to the "expander" type. I.e. the only CXL devices using the CXL core presently are those implementing the CXL 2.0 Type-3 memory expander device class code that the cxl_pci driver claims. Signed-off-by: Dan Williams <dan.j.williams@intel.com> --- drivers/cxl/core/hdm.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-)