@@ -382,6 +382,29 @@ int dw_pcie_host_init(struct pcie_port *pp)
pp->msi_irq[0] = irq;
}
+ if (pp->has_split_msi_irq) {
+ char irq_name[] = "msiXXX";
+ int irq;
+
+ for (ctrl = 1; ctrl < num_ctrls; ctrl++) {
+ if (pp->msi_irq[ctrl])
+ continue;
+
+ snprintf(irq_name, sizeof(irq_name), "msi%d", ctrl + 1);
+ irq = platform_get_irq_byname_optional(pdev, irq_name);
+ if (irq == -ENXIO) {
+ num_ctrls = ctrl;
+ pp->num_vectors = num_ctrls * MAX_MSI_IRQS_PER_CTRL;
+ dev_warn(dev, "Limiting amount of MSI irqs to %d\n", pp->num_vectors);
+ break;
+ }
+ if (irq < 0)
+ return irq;
+
+ pp->msi_irq[ctrl] = irq;
+ }
+ }
+
pp->msi_irq_chip = &dw_pci_msi_bottom_irq_chip;
ret = dw_pcie_allocate_domains(pp);
@@ -179,6 +179,7 @@ struct dw_pcie_host_ops {
struct pcie_port {
bool has_msi_ctrl:1;
+ bool has_split_msi_irq:1;
u64 cfg0_base;
void __iomem *va_cfg0_base;
u32 cfg0_size;
DWC driver parses a single "msi" interrupt which gets fired when the EP sends an MSI interrupt, however for some devices (Qualcomm) MSI vectors are handled in groups by 32 vectors in each group. Add support for parsing "split" MSI interrupts. In addition to the "msi" interrupt, the code will lookup the "msi2", "msi3", etc. IRQs and use them for the MSI group interrupts. For backwards compatibility with existing DTS files, the code will not error out if these interrupts are missing. Instead it will limit itself to the number of MSI group IRQs declared in the DT file. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- .../pci/controller/dwc/pcie-designware-host.c | 23 +++++++++++++++++++ drivers/pci/controller/dwc/pcie-designware.h | 1 + 2 files changed, 24 insertions(+)