| Message ID | 20220313000824.229405-6-dmitry.baryshkov@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | PCI: qcom: rework pipe_clk/pipe_clk_src handling | expand |
On Sat 12 Mar 18:08 CST 2022, Dmitry Baryshkov wrote: > Manual reparenting of pipe_clk_src is being replaced with the parking of > the clock with clk_disable()/clk_enable(). Drop redundant code letting > the pipe clock driver park the clock to the safe bi_tcxo parent > automatically. > > Cc: Prasad Malisetty <quic_pmaliset@quicinc.com> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Regards, Bjorn > --- > drivers/pci/controller/dwc/pcie-qcom.c | 39 +------------------------- > 1 file changed, 1 insertion(+), 38 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c > index a6becafb6a77..b48c899bcc97 100644 > --- a/drivers/pci/controller/dwc/pcie-qcom.c > +++ b/drivers/pci/controller/dwc/pcie-qcom.c > @@ -164,9 +164,6 @@ struct qcom_pcie_resources_2_7_0 { > int num_clks; > struct regulator_bulk_data supplies[2]; > struct reset_control *pci_reset; > - struct clk *pipe_clk_src; > - struct clk *phy_pipe_clk; > - struct clk *ref_clk_src; > }; > > union qcom_pcie_resources { > @@ -192,7 +189,6 @@ struct qcom_pcie_ops { > > struct qcom_pcie_cfg { > const struct qcom_pcie_ops *ops; > - unsigned int pipe_clk_need_muxing:1; > unsigned int has_tbu_clk:1; > unsigned int has_ddrss_sf_tbu_clk:1; > unsigned int has_aggre0_clk:1; > @@ -1158,20 +1154,6 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) > if (ret < 0) > return ret; > > - if (pcie->cfg->pipe_clk_need_muxing) { > - res->pipe_clk_src = devm_clk_get(dev, "pipe_mux"); > - if (IS_ERR(res->pipe_clk_src)) > - return PTR_ERR(res->pipe_clk_src); > - > - res->phy_pipe_clk = devm_clk_get(dev, "phy_pipe"); > - if (IS_ERR(res->phy_pipe_clk)) > - return PTR_ERR(res->phy_pipe_clk); > - > - res->ref_clk_src = devm_clk_get(dev, "ref"); > - if (IS_ERR(res->ref_clk_src)) > - return PTR_ERR(res->ref_clk_src); > - } > - > return 0; > } > > @@ -1189,10 +1171,6 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) > return ret; > } > > - /* Set TCXO as clock source for pcie_pipe_clk_src */ > - if (pcie->cfg->pipe_clk_need_muxing) > - clk_set_parent(res->pipe_clk_src, res->ref_clk_src); > - > ret = clk_bulk_prepare_enable(res->num_clks, res->clks); > if (ret < 0) > goto err_disable_regulators; > @@ -1254,18 +1232,8 @@ static void qcom_pcie_deinit_2_7_0(struct qcom_pcie *pcie) > struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; > > clk_bulk_disable_unprepare(res->num_clks, res->clks); > - regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); > -} > > -static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie) > -{ > - struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; > - > - /* Set pipe clock as clock source for pcie_pipe_clk_src */ > - if (pcie->cfg->pipe_clk_need_muxing) > - clk_set_parent(res->pipe_clk_src, res->phy_pipe_clk); > - > - return 0; > + regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); > } > > static int qcom_pcie_link_up(struct dw_pcie *pci) > @@ -1441,7 +1409,6 @@ static const struct qcom_pcie_ops ops_2_7_0 = { > .init = qcom_pcie_init_2_7_0, > .deinit = qcom_pcie_deinit_2_7_0, > .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, > - .post_init = qcom_pcie_post_init_2_7_0, > }; > > /* Qcom IP rev.: 1.9.0 */ > @@ -1450,7 +1417,6 @@ static const struct qcom_pcie_ops ops_1_9_0 = { > .init = qcom_pcie_init_2_7_0, > .deinit = qcom_pcie_deinit_2_7_0, > .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, > - .post_init = qcom_pcie_post_init_2_7_0, > .config_sid = qcom_pcie_config_sid_sm8250, > }; > > @@ -1488,7 +1454,6 @@ static const struct qcom_pcie_cfg sm8250_cfg = { > static const struct qcom_pcie_cfg sm8450_pcie0_cfg = { > .ops = &ops_1_9_0, > .has_ddrss_sf_tbu_clk = true, > - .pipe_clk_need_muxing = true, > .has_aggre0_clk = true, > .has_aggre1_clk = true, > }; > @@ -1496,14 +1461,12 @@ static const struct qcom_pcie_cfg sm8450_pcie0_cfg = { > static const struct qcom_pcie_cfg sm8450_pcie1_cfg = { > .ops = &ops_1_9_0, > .has_ddrss_sf_tbu_clk = true, > - .pipe_clk_need_muxing = true, > .has_aggre1_clk = true, > }; > > static const struct qcom_pcie_cfg sc7280_cfg = { > .ops = &ops_1_9_0, > .has_tbu_clk = true, > - .pipe_clk_need_muxing = true, > }; > > static const struct dw_pcie_ops dw_pcie_ops = { > -- > 2.34.1 >
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index a6becafb6a77..b48c899bcc97 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -164,9 +164,6 @@ struct qcom_pcie_resources_2_7_0 { int num_clks; struct regulator_bulk_data supplies[2]; struct reset_control *pci_reset; - struct clk *pipe_clk_src; - struct clk *phy_pipe_clk; - struct clk *ref_clk_src; }; union qcom_pcie_resources { @@ -192,7 +189,6 @@ struct qcom_pcie_ops { struct qcom_pcie_cfg { const struct qcom_pcie_ops *ops; - unsigned int pipe_clk_need_muxing:1; unsigned int has_tbu_clk:1; unsigned int has_ddrss_sf_tbu_clk:1; unsigned int has_aggre0_clk:1; @@ -1158,20 +1154,6 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) if (ret < 0) return ret; - if (pcie->cfg->pipe_clk_need_muxing) { - res->pipe_clk_src = devm_clk_get(dev, "pipe_mux"); - if (IS_ERR(res->pipe_clk_src)) - return PTR_ERR(res->pipe_clk_src); - - res->phy_pipe_clk = devm_clk_get(dev, "phy_pipe"); - if (IS_ERR(res->phy_pipe_clk)) - return PTR_ERR(res->phy_pipe_clk); - - res->ref_clk_src = devm_clk_get(dev, "ref"); - if (IS_ERR(res->ref_clk_src)) - return PTR_ERR(res->ref_clk_src); - } - return 0; } @@ -1189,10 +1171,6 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) return ret; } - /* Set TCXO as clock source for pcie_pipe_clk_src */ - if (pcie->cfg->pipe_clk_need_muxing) - clk_set_parent(res->pipe_clk_src, res->ref_clk_src); - ret = clk_bulk_prepare_enable(res->num_clks, res->clks); if (ret < 0) goto err_disable_regulators; @@ -1254,18 +1232,8 @@ static void qcom_pcie_deinit_2_7_0(struct qcom_pcie *pcie) struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; clk_bulk_disable_unprepare(res->num_clks, res->clks); - regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); -} -static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie) -{ - struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; - - /* Set pipe clock as clock source for pcie_pipe_clk_src */ - if (pcie->cfg->pipe_clk_need_muxing) - clk_set_parent(res->pipe_clk_src, res->phy_pipe_clk); - - return 0; + regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); } static int qcom_pcie_link_up(struct dw_pcie *pci) @@ -1441,7 +1409,6 @@ static const struct qcom_pcie_ops ops_2_7_0 = { .init = qcom_pcie_init_2_7_0, .deinit = qcom_pcie_deinit_2_7_0, .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, - .post_init = qcom_pcie_post_init_2_7_0, }; /* Qcom IP rev.: 1.9.0 */ @@ -1450,7 +1417,6 @@ static const struct qcom_pcie_ops ops_1_9_0 = { .init = qcom_pcie_init_2_7_0, .deinit = qcom_pcie_deinit_2_7_0, .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, - .post_init = qcom_pcie_post_init_2_7_0, .config_sid = qcom_pcie_config_sid_sm8250, }; @@ -1488,7 +1454,6 @@ static const struct qcom_pcie_cfg sm8250_cfg = { static const struct qcom_pcie_cfg sm8450_pcie0_cfg = { .ops = &ops_1_9_0, .has_ddrss_sf_tbu_clk = true, - .pipe_clk_need_muxing = true, .has_aggre0_clk = true, .has_aggre1_clk = true, }; @@ -1496,14 +1461,12 @@ static const struct qcom_pcie_cfg sm8450_pcie0_cfg = { static const struct qcom_pcie_cfg sm8450_pcie1_cfg = { .ops = &ops_1_9_0, .has_ddrss_sf_tbu_clk = true, - .pipe_clk_need_muxing = true, .has_aggre1_clk = true, }; static const struct qcom_pcie_cfg sc7280_cfg = { .ops = &ops_1_9_0, .has_tbu_clk = true, - .pipe_clk_need_muxing = true, }; static const struct dw_pcie_ops dw_pcie_ops = {
Manual reparenting of pipe_clk_src is being replaced with the parking of the clock with clk_disable()/clk_enable(). Drop redundant code letting the pipe clock driver park the clock to the safe bi_tcxo parent automatically. Cc: Prasad Malisetty <quic_pmaliset@quicinc.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/pci/controller/dwc/pcie-qcom.c | 39 +------------------------- 1 file changed, 1 insertion(+), 38 deletions(-)