From patchwork Sat Nov 27 01:22:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 1560552 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=linutronix.de header.i=@linutronix.de header.a=rsa-sha256 header.s=2020 header.b=tXVYQnTV; dkim=pass header.d=linutronix.de header.i=@linutronix.de header.a=ed25519-sha256 header.s=2020e header.b=PrxvQQcO; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4J1DYD4BYSz9sRR for ; Sat, 27 Nov 2021 12:29:20 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350492AbhK0Bcc (ORCPT ); Fri, 26 Nov 2021 20:32:32 -0500 Received: from Galois.linutronix.de ([193.142.43.55]:40214 "EHLO galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345861AbhK0Bab (ORCPT ); Fri, 26 Nov 2021 20:30:31 -0500 Message-ID: <20211126232734.828800907@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1637976161; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=jqtFVAM7PnL3sv4Z1HtzZW/zRECsX5MQXu0tEubArI4=; b=tXVYQnTV1Bx49dMwZFM5YcOx5fBlNJ+2qXjFrY2lEpKWe6n9fBRU3u8B1+iwPt5BtBst2V awIE9+bfvUSqJfcP3fFekAr407YSp84K0U8SXwyuRRjKLBSQ8BXUwewW0NJIJlEgD1vX34 1jQIyVgHIMvdQlKYi5zloNedqy/gr1F7+0wk+6OgcBw6w37d24soI2HfGRKgapR0pSJ9YZ cMOeKAXO3HmNzwZ65NaIDe63p1r7OzA831d1hzH7fqWRvJ/SFeFRSiZNo+AndDF6INU35a vF0OWE0xdyUFzfuk8vSxUAsSVYbrcl/4Qm/5A2zgUbctRyCUnC3O+w2wsqQrHw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1637976161; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=jqtFVAM7PnL3sv4Z1HtzZW/zRECsX5MQXu0tEubArI4=; b=PrxvQQcOyByRp5Tu0ZVjqcEqITEzYqneFzk16gbo/3sILcWfwqH/DQ1WASepnVft9ACeyh 9b/Paf8IZ6IYdMBw== From: Thomas Gleixner To: LKML Cc: Bjorn Helgaas , Marc Zygnier , Alex Williamson , Kevin Tian , Jason Gunthorpe , Megha Dey , Ashok Raj , linux-pci@vger.kernel.org, Greg Kroah-Hartman , linux-s390@vger.kernel.org, Heiko Carstens , Christian Borntraeger , Jon Mason , Dave Jiang , Allen Hubbe , linux-ntb@googlegroups.com Subject: [patch 09/32] PCI/MSI: Use msi_add_msi_desc() References: <20211126230957.239391799@linutronix.de> MIME-Version: 1.0 Date: Sat, 27 Nov 2021 02:22:41 +0100 (CET) Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Simplify the allocation of MSI descriptors by using msi_add_msi_desc() which moves the storage handling to core code and prepares for dynamic extension of the MSI-X vector space. Signed-off-by: Thomas Gleixner --- drivers/pci/msi/msi.c | 121 ++++++++++++++++++++++++-------------------------- 1 file changed, 59 insertions(+), 62 deletions(-) --- a/drivers/pci/msi/msi.c +++ b/drivers/pci/msi/msi.c @@ -340,43 +340,49 @@ void pci_restore_msi_state(struct pci_de } EXPORT_SYMBOL_GPL(pci_restore_msi_state); -static struct msi_desc * -msi_setup_entry(struct pci_dev *dev, int nvec, struct irq_affinity_desc *masks) +static int msi_setup_msi_desc(struct pci_dev *dev, int nvec, + struct irq_affinity_desc *masks) { - struct msi_desc *entry; + struct msi_desc desc; u16 control; + int ret; /* MSI Entry Initialization */ - entry = alloc_msi_entry(&dev->dev, nvec, masks); - if (!entry) - return NULL; + memset(&desc, 0, sizeof(desc)); pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); /* Lies, damned lies, and MSIs */ if (dev->dev_flags & PCI_DEV_FLAGS_HAS_MSI_MASKING) control |= PCI_MSI_FLAGS_MASKBIT; + /* Respect XEN's mask disabling */ + if (pci_msi_ignore_mask) + control &= ~PCI_MSI_FLAGS_MASKBIT; - entry->pci.msi_attrib.is_64 = !!(control & PCI_MSI_FLAGS_64BIT); - entry->pci.msi_attrib.can_mask = !pci_msi_ignore_mask && - !!(control & PCI_MSI_FLAGS_MASKBIT); - entry->pci.msi_attrib.default_irq = dev->irq; - entry->pci.msi_attrib.multi_cap = (control & PCI_MSI_FLAGS_QMASK) >> 1; - entry->pci.msi_attrib.multiple = ilog2(__roundup_pow_of_two(nvec)); + desc.nvec_used = nvec; + desc.pci.msi_attrib.is_64 = !!(control & PCI_MSI_FLAGS_64BIT); + desc.pci.msi_attrib.can_mask = !!(control & PCI_MSI_FLAGS_MASKBIT); + desc.pci.msi_attrib.default_irq = dev->irq; + desc.pci.msi_attrib.multi_cap = (control & PCI_MSI_FLAGS_QMASK) >> 1; + desc.pci.msi_attrib.multiple = ilog2(__roundup_pow_of_two(nvec)); + desc.affinity = masks; if (control & PCI_MSI_FLAGS_64BIT) - entry->pci.mask_pos = dev->msi_cap + PCI_MSI_MASK_64; + desc.pci.mask_pos = dev->msi_cap + PCI_MSI_MASK_64; else - entry->pci.mask_pos = dev->msi_cap + PCI_MSI_MASK_32; + desc.pci.mask_pos = dev->msi_cap + PCI_MSI_MASK_32; /* Save the initial mask status */ - if (entry->pci.msi_attrib.can_mask) - pci_read_config_dword(dev, entry->pci.mask_pos, &entry->pci.msi_mask); + if (desc.pci.msi_attrib.can_mask) + pci_read_config_dword(dev, desc.pci.mask_pos, &desc.pci.msi_mask); - dev->dev.msi.data->properties = MSI_PROP_PCI_MSI; - if (entry->pci.msi_attrib.is_64) - dev->dev.msi.data->properties |= MSI_PROP_64BIT; + ret = msi_add_msi_desc(&dev->dev, &desc); + if (!ret) { + dev->dev.msi.data->properties = MSI_PROP_PCI_MSI; + if (desc.pci.msi_attrib.is_64) + dev->dev.msi.data->properties |= MSI_PROP_64BIT; + } - return entry; + return ret; } static int msi_verify_entries(struct pci_dev *dev) @@ -421,17 +427,14 @@ static int msi_capability_init(struct pc masks = irq_create_affinity_masks(nvec, affd); msi_lock_descs(&dev->dev); - entry = msi_setup_entry(dev, nvec, masks); - if (!entry) { - ret = -ENOMEM; + ret = msi_setup_msi_desc(dev, nvec, masks); + if (ret) goto unlock; - } /* All MSIs are unmasked by default; mask them all */ + entry = first_pci_msi_entry(dev); pci_msi_mask(entry, msi_multi_mask(entry)); - list_add_tail(&entry->list, dev_to_msi_list(&dev->dev)); - /* Configure MSI capability structure */ ret = pci_msi_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI); if (ret) @@ -480,49 +483,41 @@ static void __iomem *msix_map_region(str return ioremap(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE); } -static int msix_setup_entries(struct pci_dev *dev, void __iomem *base, - struct msix_entry *entries, int nvec, - struct irq_affinity_desc *masks) +static int msix_setup_msi_descs(struct pci_dev *dev, void __iomem *base, + struct msix_entry *entries, int nvec, + struct irq_affinity_desc *masks) { - int i, vec_count = pci_msix_vec_count(dev); + int ret, i, vec_count = pci_msix_vec_count(dev); struct irq_affinity_desc *curmsk; - struct msi_desc *entry; + struct msi_desc desc; void __iomem *addr; - for (i = 0, curmsk = masks; i < nvec; i++) { - entry = alloc_msi_entry(&dev->dev, 1, curmsk); - if (!entry) { - /* No enough memory. Don't try again */ - return -ENOMEM; - } - - entry->pci.msi_attrib.is_msix = 1; - entry->pci.msi_attrib.is_64 = 1; - - if (entries) - entry->msi_index = entries[i].entry; - else - entry->msi_index = i; - - entry->pci.msi_attrib.is_virtual = entry->msi_index >= vec_count; - - entry->pci.msi_attrib.can_mask = !pci_msi_ignore_mask && - !entry->pci.msi_attrib.is_virtual; - - entry->pci.msi_attrib.default_irq = dev->irq; - entry->pci.mask_base = base; + memset(&desc, 0, sizeof(desc)); - if (entry->pci.msi_attrib.can_mask) { - addr = pci_msix_desc_addr(entry); - entry->pci.msix_ctrl = readl(addr + PCI_MSIX_ENTRY_VECTOR_CTRL); + desc.nvec_used = 1; + desc.pci.msi_attrib.is_msix = 1; + desc.pci.msi_attrib.is_64 = 1; + desc.pci.msi_attrib.default_irq = dev->irq; + desc.pci.mask_base = base; + + for (i = 0, curmsk = masks; i < nvec; i++, curmsk++) { + desc.msi_index = entries ? entries[i].entry : i; + desc.affinity = masks ? curmsk : NULL; + desc.pci.msi_attrib.is_virtual = desc.msi_index >= vec_count; + desc.pci.msi_attrib.can_mask = !pci_msi_ignore_mask && + !desc.pci.msi_attrib.is_virtual; + + if (!desc.pci.msi_attrib.can_mask) { + addr = pci_msix_desc_addr(&desc); + desc.pci.msix_ctrl = readl(addr + PCI_MSIX_ENTRY_VECTOR_CTRL); } - list_add_tail(&entry->list, dev_to_msi_list(&dev->dev)); - if (masks) - curmsk++; + ret = msi_add_msi_desc(&dev->dev, &desc); + if (ret) + break; } - dev->dev.msi.data->properties = MSI_PROP_PCI_MSIX | MSI_PROP_64BIT; - return 0; + + return ret; } static void msix_update_entries(struct pci_dev *dev, struct msix_entry *entries) @@ -560,10 +555,12 @@ static int msix_setup_interrupts(struct masks = irq_create_affinity_masks(nvec, affd); msi_lock_descs(&dev->dev); - ret = msix_setup_entries(dev, base, entries, nvec, masks); + ret = msix_setup_msi_descs(dev, base, entries, nvec, masks); if (ret) goto out_free; + dev->dev.msi.data->properties = MSI_PROP_PCI_MSIX | MSI_PROP_64BIT; + ret = pci_msi_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX); if (ret) goto out_free;