| Message ID | 20200907053801.22149-6-Zhiqiang.Hou@nxp.com |
|---|---|
| State | New |
| Headers | show |
| Series | PCI: layerscape: Add power management support | expand |
On Mon, 07 Sep 2020 13:37:59 +0800, Zhiqiang Hou wrote: > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> > > Update the description of the second entry of 'fsl,pcie-scfg' property, > as the LS1043A PCIe controller also has some control registers in SCFG > block, while it has 3 controllers. > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> > --- > Documentation/devicetree/bindings/pci/layerscape-pci.txt | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > Acked-by: Rob Herring <robh@kernel.org>
Hi Rob, Thanks a lot for your review and ack! Regards, Zhiqiang > -----Original Message----- > From: Rob Herring <robh@kernel.org> > Sent: 2020年9月15日 9:31 > To: Z.q. Hou <zhiqiang.hou@nxp.com> > Cc: linux-pci@vger.kernel.org; linux-kernel@vger.kernel.org; M.h. Lian > <minghuan.lian@nxp.com>; devicetree@vger.kernel.org; > gustavo.pimentel@synopsys.com; robh+dt@kernel.org; Mingkai Hu > <mingkai.hu@nxp.com>; Roy Zang <roy.zang@nxp.com>; > shawnguo@kernel.org; Leo Li <leoyang.li@nxp.com>; > bhelgaas@google.com; lorenzo.pieralisi@arm.com > Subject: Re: [PATCH 5/7] dt-bindings: pci: layerscape-pci: Update the > description of SCFG property > > On Mon, 07 Sep 2020 13:37:59 +0800, Zhiqiang Hou wrote: > > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> > > > > Update the description of the second entry of 'fsl,pcie-scfg' > > property, as the LS1043A PCIe controller also has some control > > registers in SCFG block, while it has 3 controllers. > > > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> > > --- > > Documentation/devicetree/bindings/pci/layerscape-pci.txt | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > Acked-by: Rob Herring <robh@kernel.org>
diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt index 2236d3f3089b..e992ec712bf6 100644 --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt @@ -31,7 +31,7 @@ Required properties: "intr": The interrupt that is asserted for controller interrupts - fsl,pcie-scfg: Must include two entries. The first entry must be a link to the SCFG device node - The second entry must be '0' or '1' based on physical PCIe controller index. + The second entry is the physical PCIe controller index starting from '0'. This is used to get SCFG PEXN registers - dma-coherent: Indicates that the hardware IP block can ensure the coherency of the data transferred from/to the IP block. This can avoid the software