| Message ID | 20200424153858.29744-9-pali@kernel.org |
|---|---|
| State | New |
| Headers | show |
| Series | PCI: aardvark: Fix support for Turris MOX and Compex wifi cards | expand |
On Fri, Apr 24, 2020 at 05:38:54PM +0200, Pali Rohár wrote: > PCI-E capability macros are already defined in linux/pci_regs.h. > Remove their reimplementation in pcie-aardvark. s/PCI-E/PCIe/ but only if you need to repost this for some other reason. Thanks a lot for doing this! I noticed this while reading through the driver earlier. Using the normal names definitely makes this a lot more readable and greppable. > Signed-off-by: Pali Rohár <pali@kernel.org> > --- > drivers/pci/controller/pci-aardvark.c | 41 ++++++++++++--------------- > 1 file changed, 18 insertions(+), 23 deletions(-) > > diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c > index 7a4f395c5812..948e61e76053 100644 > --- a/drivers/pci/controller/pci-aardvark.c > +++ b/drivers/pci/controller/pci-aardvark.c > @@ -34,17 +34,6 @@ > #define PCIE_CORE_CMD_MEM_IO_REQ_EN BIT(2) > #define PCIE_CORE_DEV_REV_REG 0x8 > #define PCIE_CORE_PCIEXP_CAP 0xc0 > -#define PCIE_CORE_DEV_CTRL_STATS_REG 0xc8 > -#define PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE (0 << 4) > -#define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT 5 > -#define PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE (0 << 11) > -#define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT 12 > -#define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ 0x2 > -#define PCIE_CORE_LINK_CTRL_STAT_REG 0xd0 > -#define PCIE_CORE_LINK_L0S_ENTRY BIT(0) > -#define PCIE_CORE_LINK_TRAINING BIT(5) > -#define PCIE_CORE_LINK_SPEED_SHIFT 16 > -#define PCIE_CORE_LINK_WIDTH_SHIFT 20 > #define PCIE_CORE_ERR_CAPCTL_REG 0x118 > #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX BIT(5) > #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN BIT(6) > @@ -223,6 +212,11 @@ static inline u32 advk_readl(struct advk_pcie *pcie, u64 reg) > return readl(pcie->base + reg); > } > > +static inline u16 advk_read16(struct advk_pcie *pcie, u64 reg) > +{ > + return advk_readl(pcie, (reg & ~0x3)) >> ((reg & 0x3) * 8); > +} > + > static int advk_pcie_link_up(struct advk_pcie *pcie) > { > u32 val, ltssm_state; > @@ -286,16 +280,16 @@ static int advk_pcie_train_at_gen(struct advk_pcie *pcie, int gen) > * Start link training immediately after enabling it. > * This solves problems for some buggy cards. > */ > - reg = advk_readl(pcie, PCIE_CORE_LINK_CTRL_STAT_REG); > - reg |= PCIE_CORE_LINK_TRAINING; > - advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG); > + reg = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_LNKCTL); > + reg |= PCI_EXP_LNKCTL_RL; > + advk_writel(pcie, reg, PCIE_CORE_PCIEXP_CAP + PCI_EXP_LNKCTL); > > ret = advk_pcie_wait_for_link(pcie); > if (ret) > return ret; > > - reg = advk_readl(pcie, PCIE_CORE_LINK_CTRL_STAT_REG); > - neg_gen = (reg >> PCIE_CORE_LINK_SPEED_SHIFT) & 0xf; > + reg = advk_read16(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_LNKSTA); > + neg_gen = reg & PCI_EXP_LNKSTA_CLS; > > return neg_gen; > } > @@ -385,13 +379,14 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie) > PCIE_CORE_ERR_CAPCTL_ECRC_CHCK_RCV; > advk_writel(pcie, reg, PCIE_CORE_ERR_CAPCTL_REG); > > - /* Set PCIe Device Control and Status 1 PF0 register */ > - reg = PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE | > - (7 << PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT) | > - PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE | > - (PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ << > - PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT); > - advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG); > + /* Set PCIe Device Control register */ > + reg = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL); > + reg &= ~PCI_EXP_DEVCTL_RELAX_EN; > + reg &= ~PCI_EXP_DEVCTL_NOSNOOP_EN; > + reg &= ~PCI_EXP_DEVCTL_READRQ; > + reg |= PCI_EXP_DEVCTL_PAYLOAD; /* Set max payload size */ > + reg |= PCI_EXP_DEVCTL_READRQ_512B; > + advk_writel(pcie, reg, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL); > > /* Program PCIe Control 2 to disable strict ordering */ > reg = PCIE_CORE_CTRL2_RESERVED | > -- > 2.20.1 >
diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index 7a4f395c5812..948e61e76053 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -34,17 +34,6 @@ #define PCIE_CORE_CMD_MEM_IO_REQ_EN BIT(2) #define PCIE_CORE_DEV_REV_REG 0x8 #define PCIE_CORE_PCIEXP_CAP 0xc0 -#define PCIE_CORE_DEV_CTRL_STATS_REG 0xc8 -#define PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE (0 << 4) -#define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT 5 -#define PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE (0 << 11) -#define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT 12 -#define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ 0x2 -#define PCIE_CORE_LINK_CTRL_STAT_REG 0xd0 -#define PCIE_CORE_LINK_L0S_ENTRY BIT(0) -#define PCIE_CORE_LINK_TRAINING BIT(5) -#define PCIE_CORE_LINK_SPEED_SHIFT 16 -#define PCIE_CORE_LINK_WIDTH_SHIFT 20 #define PCIE_CORE_ERR_CAPCTL_REG 0x118 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX BIT(5) #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN BIT(6) @@ -223,6 +212,11 @@ static inline u32 advk_readl(struct advk_pcie *pcie, u64 reg) return readl(pcie->base + reg); } +static inline u16 advk_read16(struct advk_pcie *pcie, u64 reg) +{ + return advk_readl(pcie, (reg & ~0x3)) >> ((reg & 0x3) * 8); +} + static int advk_pcie_link_up(struct advk_pcie *pcie) { u32 val, ltssm_state; @@ -286,16 +280,16 @@ static int advk_pcie_train_at_gen(struct advk_pcie *pcie, int gen) * Start link training immediately after enabling it. * This solves problems for some buggy cards. */ - reg = advk_readl(pcie, PCIE_CORE_LINK_CTRL_STAT_REG); - reg |= PCIE_CORE_LINK_TRAINING; - advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG); + reg = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_LNKCTL); + reg |= PCI_EXP_LNKCTL_RL; + advk_writel(pcie, reg, PCIE_CORE_PCIEXP_CAP + PCI_EXP_LNKCTL); ret = advk_pcie_wait_for_link(pcie); if (ret) return ret; - reg = advk_readl(pcie, PCIE_CORE_LINK_CTRL_STAT_REG); - neg_gen = (reg >> PCIE_CORE_LINK_SPEED_SHIFT) & 0xf; + reg = advk_read16(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_LNKSTA); + neg_gen = reg & PCI_EXP_LNKSTA_CLS; return neg_gen; } @@ -385,13 +379,14 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie) PCIE_CORE_ERR_CAPCTL_ECRC_CHCK_RCV; advk_writel(pcie, reg, PCIE_CORE_ERR_CAPCTL_REG); - /* Set PCIe Device Control and Status 1 PF0 register */ - reg = PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE | - (7 << PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT) | - PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE | - (PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ << - PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT); - advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG); + /* Set PCIe Device Control register */ + reg = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL); + reg &= ~PCI_EXP_DEVCTL_RELAX_EN; + reg &= ~PCI_EXP_DEVCTL_NOSNOOP_EN; + reg &= ~PCI_EXP_DEVCTL_READRQ; + reg |= PCI_EXP_DEVCTL_PAYLOAD; /* Set max payload size */ + reg |= PCI_EXP_DEVCTL_READRQ_512B; + advk_writel(pcie, reg, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL); /* Program PCIe Control 2 to disable strict ordering */ reg = PCIE_CORE_CTRL2_RESERVED |
PCI-E capability macros are already defined in linux/pci_regs.h. Remove their reimplementation in pcie-aardvark. Signed-off-by: Pali Rohár <pali@kernel.org> --- drivers/pci/controller/pci-aardvark.c | 41 ++++++++++++--------------- 1 file changed, 18 insertions(+), 23 deletions(-)