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[79.53.232.203]) by smtp.googlemail.com with ESMTPSA id y13sm172916eje.3.2020.03.20.11.35.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Mar 2020 11:35:28 -0700 (PDT) From: Ansuel Smith To: Stanimir Varbanov Cc: Sham Muthayyan , Ansuel Smith , Andy Gross , Bjorn Andersson , Bjorn Helgaas , Rob Herring , Mark Rutland , Lorenzo Pieralisi , Andrew Murray , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 10/12] pcie: qcom: add Force GEN1 support Date: Fri, 20 Mar 2020 19:34:52 +0100 Message-Id: <20200320183455.21311-10-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200320183455.21311-1-ansuelsmth@gmail.com> References: <20200320183455.21311-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Sham Muthayyan Add Force GEN1 support needed in some ipq806x board that needs to limit some pcie line to gen1 for some hardware limitation Signed-off-by: Sham Muthayyan Signed-off-by: Ansuel Smith --- drivers/pci/controller/dwc/pcie-qcom.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index e26ba8f63d4f..03130a3206b4 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -123,6 +123,8 @@ #define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE 0x358 #define SLV_ADDR_SPACE_SZ 0x10000000 +#define PCIE20_LNK_CONTROL2_LINK_STATUS2 0xA0 + #define DEVICE_TYPE_RC 0x4 #define QCOM_PCIE_2_1_0_MAX_SUPPLY 3 @@ -223,6 +225,7 @@ struct qcom_pcie { struct phy *phy; struct gpio_desc *reset; const struct qcom_pcie_ops *ops; + uint32_t force_gen1; }; #define to_qcom_pcie(x) dev_get_drvdata((x)->dev) @@ -515,6 +518,11 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) /* wait for clock acquisition */ usleep_range(1000, 1500); + if (pcie->force_gen1) { + writel_relaxed((readl_relaxed( + pcie->pci->dbi_base + PCIE20_LNK_CONTROL2_LINK_STATUS2) | 1), + pcie->pci->dbi_base + PCIE20_LNK_CONTROL2_LINK_STATUS2); + } /* Set the Max TLP size to 2K, instead of using default of 4K */ @@ -1487,6 +1495,8 @@ static int qcom_pcie_probe(struct platform_device *pdev) struct dw_pcie *pci; struct qcom_pcie *pcie; int ret; + uint32_t force_gen1 = 0; + struct device_node *np = pdev->dev.of_node; pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); if (!pcie) @@ -1517,6 +1527,9 @@ static int qcom_pcie_probe(struct platform_device *pdev) goto err_pm_runtime_put; } + of_property_read_u32(np, "force_gen1", &force_gen1); + pcie->force_gen1 = force_gen1; + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "parf"); pcie->parf = devm_ioremap_resource(dev, res); if (IS_ERR(pcie->parf)) {