| Message ID | 20191224173942.18160-5-repk@triplefau.lt |
|---|---|
| State | New |
| Headers | show |
| Series | PCI: amlogic: Make PCIe working reliably on AXG platforms | expand |
On Tue, Dec 24, 2019 at 06:39:41PM +0100, Remi Pommarel wrote: > Now that a new PHYs has been introduced for AXG SoC family, update > dt bindings documentation. This breaks compatibility. If that's okay, say so and why it is. If only someone had said putting the phy here in the first place was wrong: https://lore.kernel.org/linux-amlogic/20180829004122.GA25928@bogus/ > > Signed-off-by: Remi Pommarel <repk@triplefau.lt> > --- > .../bindings/pci/amlogic,meson-pcie.txt | 22 ++++++++----------- > 1 file changed, 9 insertions(+), 13 deletions(-) > > diff --git a/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt > index 84fdc422792e..b6acbe694ffb 100644 > --- a/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt > +++ b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt > @@ -18,7 +18,6 @@ Required properties: > - reg-names: Must be > - "elbi" External local bus interface registers > - "cfg" Meson specific registers > - - "phy" Meson PCIE PHY registers for AXG SoC Family > - "config" PCIe configuration space > - reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal. > - clocks: Must contain an entry for each entry in clock-names. > @@ -26,13 +25,13 @@ Required properties: > - "pclk" PCIe GEN 100M PLL clock > - "port" PCIe_x(A or B) RC clock gate > - "general" PCIe Phy clock > - - "mipi" PCIe_x(A or B) 100M ref clock gate for AXG SoC Family > - resets: phandle to the reset lines. > -- reset-names: must contain "phy" "port" and "apb" > - - "phy" Share PHY reset for AXG SoC Family > +- reset-names: must contain "port" and "apb" > - "port" Port A or B reset > - "apb" Share APB reset > -- phys: should contain a phandle to the shared phy for G12A SoC Family > +- phys: should contain a phandle to the PCIE phy > +- phy-names: must contain "pcie" > + > - device_type: > should be "pci". As specified in designware-pcie.txt > > @@ -43,9 +42,8 @@ Example configuration: > compatible = "amlogic,axg-pcie", "snps,dw-pcie"; > reg = <0x0 0xf9800000 0x0 0x400000 > 0x0 0xff646000 0x0 0x2000 > - 0x0 0xff644000 0x0 0x2000 > 0x0 0xf9f00000 0x0 0x100000>; > - reg-names = "elbi", "cfg", "phy", "config"; > + reg-names = "elbi", "cfg", "config"; > reset-gpios = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>; > interrupts = <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>; > #interrupt-cells = <1>; > @@ -58,17 +56,15 @@ Example configuration: > ranges = <0x82000000 0 0 0x0 0xf9c00000 0 0x00300000>; > > clocks = <&clkc CLKID_USB > - &clkc CLKID_MIPI_ENABLE > &clkc CLKID_PCIE_A > &clkc CLKID_PCIE_CML_EN0>; > clock-names = "general", > - "mipi", > "pclk", > "port"; > - resets = <&reset RESET_PCIE_PHY>, > - <&reset RESET_PCIE_A>, > + resets = <&reset RESET_PCIE_A>, > <&reset RESET_PCIE_APB>; > - reset-names = "phy", > - "port", > + reset-names = "port", > "apb"; > + phys = <&pcie_phy>; > + phy-names = "pcie"; > }; > -- > 2.24.0 >
diff --git a/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt index 84fdc422792e..b6acbe694ffb 100644 --- a/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt +++ b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt @@ -18,7 +18,6 @@ Required properties: - reg-names: Must be - "elbi" External local bus interface registers - "cfg" Meson specific registers - - "phy" Meson PCIE PHY registers for AXG SoC Family - "config" PCIe configuration space - reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal. - clocks: Must contain an entry for each entry in clock-names. @@ -26,13 +25,13 @@ Required properties: - "pclk" PCIe GEN 100M PLL clock - "port" PCIe_x(A or B) RC clock gate - "general" PCIe Phy clock - - "mipi" PCIe_x(A or B) 100M ref clock gate for AXG SoC Family - resets: phandle to the reset lines. -- reset-names: must contain "phy" "port" and "apb" - - "phy" Share PHY reset for AXG SoC Family +- reset-names: must contain "port" and "apb" - "port" Port A or B reset - "apb" Share APB reset -- phys: should contain a phandle to the shared phy for G12A SoC Family +- phys: should contain a phandle to the PCIE phy +- phy-names: must contain "pcie" + - device_type: should be "pci". As specified in designware-pcie.txt @@ -43,9 +42,8 @@ Example configuration: compatible = "amlogic,axg-pcie", "snps,dw-pcie"; reg = <0x0 0xf9800000 0x0 0x400000 0x0 0xff646000 0x0 0x2000 - 0x0 0xff644000 0x0 0x2000 0x0 0xf9f00000 0x0 0x100000>; - reg-names = "elbi", "cfg", "phy", "config"; + reg-names = "elbi", "cfg", "config"; reset-gpios = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>; interrupts = <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>; #interrupt-cells = <1>; @@ -58,17 +56,15 @@ Example configuration: ranges = <0x82000000 0 0 0x0 0xf9c00000 0 0x00300000>; clocks = <&clkc CLKID_USB - &clkc CLKID_MIPI_ENABLE &clkc CLKID_PCIE_A &clkc CLKID_PCIE_CML_EN0>; clock-names = "general", - "mipi", "pclk", "port"; - resets = <&reset RESET_PCIE_PHY>, - <&reset RESET_PCIE_A>, + resets = <&reset RESET_PCIE_A>, <&reset RESET_PCIE_APB>; - reset-names = "phy", - "port", + reset-names = "port", "apb"; + phys = <&pcie_phy>; + phy-names = "pcie"; };
Now that a new PHYs has been introduced for AXG SoC family, update dt bindings documentation. Signed-off-by: Remi Pommarel <repk@triplefau.lt> --- .../bindings/pci/amlogic,meson-pcie.txt | 22 ++++++++----------- 1 file changed, 9 insertions(+), 13 deletions(-)