From patchwork Wed Jun 27 12:29:19 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vignesh Raghavendra X-Patchwork-Id: 935558 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="Vj4m4CL1"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 41G5fm4v53z9s1B for ; Thu, 28 Jun 2018 00:59:44 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965038AbeF0O7O (ORCPT ); Wed, 27 Jun 2018 10:59:14 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:43516 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752927AbeF0O7N (ORCPT ); Wed, 27 Jun 2018 10:59:13 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id w5RCSxnn056417; Wed, 27 Jun 2018 07:28:59 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1530102539; bh=RiMf3+UR+douiyEYInNUodkhkCSKhZXkOPBcoOeBMvM=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Vj4m4CL1eOnFEa4zswc9zao5UrSIjvGfSfLycs+1GRiNG+lNqRO1SZYrOiISMIHLi xIW7sFSI9R3peMe47W46dvaphZQTI7impf8oVHkVhIjhFtwVtW6TfVmm1HedgdYZUC AC8hfg0ylg36CylOCVq2fvqY6v2cR/jt4lE8O/Eg= Received: from DLEE112.ent.ti.com (dlee112.ent.ti.com [157.170.170.23]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id w5RCSxSf010766; Wed, 27 Jun 2018 07:28:59 -0500 Received: from DLEE100.ent.ti.com (157.170.170.30) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Wed, 27 Jun 2018 07:28:59 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Wed, 27 Jun 2018 07:28:58 -0500 Received: from a0132425.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id w5RCSgMv027559; Wed, 27 Jun 2018 07:28:56 -0500 From: Vignesh R To: Tony Lindgren , Rob Herring , Kishon Vijay Abraham I , Lorenzo Pieralisi CC: Bjorn Helgaas , , , , , Vignesh R Subject: [PATCH v2 4/4] ARM: dts: dra7: Fix up unaligned access setting for PCIe EP Date: Wed, 27 Jun 2018 17:59:19 +0530 Message-ID: <20180627122919.23926-5-vigneshr@ti.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180627122919.23926-1-vigneshr@ti.com> References: <20180627122919.23926-1-vigneshr@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Bit positions of PCIE_SS1_AXI2OCP_LEGACY_MODE_ENABLE and PCIE_SS1_AXI2OCP_LEGACY_MODE_ENABLE in CTRL_CORE_SMA_SW_7 are incorrectly documented in the TRM. In fact, the bit positions are swapped. Update the DT bindings for PCIe EP to reflect the same. Signed-off-by: Vignesh R --- arch/arm/boot/dts/dra7.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 7bfe7f28e3bd..27ad193e1a87 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -355,7 +355,7 @@ ti,hwmods = "pcie1"; phys = <&pcie1_phy>; phy-names = "pcie-phy0"; - ti,syscon-unaligned-access = <&scm_conf1 0x14 2>; + ti,syscon-unaligned-access = <&scm_conf1 0x14 1>; status = "disabled"; }; };