From patchwork Fri Oct 13 16:09:05 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 825555 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yDCMw5nWpz9s2G for ; Sat, 14 Oct 2017 03:09:32 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751906AbdJMQJ3 (ORCPT ); Fri, 13 Oct 2017 12:09:29 -0400 Received: from bastet.se.axis.com ([195.60.68.11]:52187 "EHLO bastet.se.axis.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751544AbdJMQJ1 (ORCPT ); Fri, 13 Oct 2017 12:09:27 -0400 Received: from localhost (localhost [127.0.0.1]) by bastet.se.axis.com (Postfix) with ESMTP id 6883218602; Fri, 13 Oct 2017 18:09:26 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at bastet.se.axis.com Received: from bastet.se.axis.com ([IPv6:::ffff:127.0.0.1]) by localhost (bastet.se.axis.com [::ffff:127.0.0.1]) (amavisd-new, port 10024) with LMTP id sPws39ZkEpy4; Fri, 13 Oct 2017 18:09:25 +0200 (CEST) Received: from boulder02.se.axis.com (boulder02.se.axis.com [10.0.8.16]) by bastet.se.axis.com (Postfix) with ESMTPS id 99A7F1847D; Fri, 13 Oct 2017 18:09:25 +0200 (CEST) Received: from boulder02.se.axis.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 7BACE1A069; Fri, 13 Oct 2017 18:09:25 +0200 (CEST) Received: from boulder02.se.axis.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 707BD1A066; Fri, 13 Oct 2017 18:09:25 +0200 (CEST) Received: from thoth.se.axis.com (unknown [10.0.2.173]) by boulder02.se.axis.com (Postfix) with ESMTP; Fri, 13 Oct 2017 18:09:25 +0200 (CEST) Received: from lnxartpec1.se.axis.com (lnxartpec1.se.axis.com [10.88.4.10]) by thoth.se.axis.com (Postfix) with ESMTP id 64046DFE; Fri, 13 Oct 2017 18:09:25 +0200 (CEST) Received: by lnxartpec1.se.axis.com (Postfix, from userid 20283) id 60419401A0; Fri, 13 Oct 2017 18:09:25 +0200 (CEST) From: Niklas Cassel To: Jingoo Han , Joao Pinto , Bjorn Helgaas Cc: Niklas Cassel , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 02/10] PCI: designware-ep: set_msi should only set MMC bits Date: Fri, 13 Oct 2017 18:09:05 +0200 Message-Id: <20171013160914.3220-3-niklas.cassel@axis.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171013160914.3220-1-niklas.cassel@axis.com> References: <20171013160914.3220-1-niklas.cassel@axis.com> X-TM-AS-GCONF: 00 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Previously, set_msi wrote all bits in the Message Control register, thus overwriting the 64 bit address capable bit. By clearing the 64 bit address capable bit, we break MSI on systems where the RC has set a 64 bit MSI address. Signed-off-by: Niklas Cassel --- drivers/pci/dwc/pcie-designware-ep.c | 4 +++- drivers/pci/dwc/pcie-designware.h | 1 + 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/pci/dwc/pcie-designware-ep.c b/drivers/pci/dwc/pcie-designware-ep.c index d53d5f168363..c92ab87fd660 100644 --- a/drivers/pci/dwc/pcie-designware-ep.c +++ b/drivers/pci/dwc/pcie-designware-ep.c @@ -220,7 +220,9 @@ static int dw_pcie_ep_set_msi(struct pci_epc *epc, u8 encode_int) struct dw_pcie_ep *ep = epc_get_drvdata(epc); struct dw_pcie *pci = to_dw_pcie_from_ep(ep); - val = (encode_int << MSI_CAP_MMC_SHIFT); + val = dw_pcie_readw_dbi(pci, MSI_MESSAGE_CONTROL); + val &= ~MSI_CAP_MMC_MASK; + val |= (encode_int << MSI_CAP_MMC_SHIFT) & MSI_CAP_MMC_MASK; dw_pcie_writew_dbi(pci, MSI_MESSAGE_CONTROL, val); return 0; diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h index 547352a317f8..36183906e1d2 100644 --- a/drivers/pci/dwc/pcie-designware.h +++ b/drivers/pci/dwc/pcie-designware.h @@ -101,6 +101,7 @@ #define MSI_MESSAGE_CONTROL 0x52 #define MSI_CAP_MMC_SHIFT 1 +#define MSI_CAP_MMC_MASK (7 << MSI_CAP_MMC_SHIFT) #define MSI_CAP_MME_SHIFT 4 #define MSI_CAP_MME_MASK (7 << MSI_CAP_MME_SHIFT) #define MSI_MESSAGE_ADDR_L32 0x54