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Mon, 13 Feb 2017 17:26:15 +0900 (KST) From: Jaehoon Chung To: linux-pci@vger.kernel.org Cc: bhelgaas@google.com, krzk@kernel.org, linux-kernel@vger.kernel.org, jingoohan1@gmail.com, javier@osg.samsung.com, kgene@kernel.org, linux-samsung-soc@vger.kernel.org, cpgs@samsung.com, niyas.ahmed@samsung.com, alim.akhtar@samsung.com, pankaj.dubey@samsung.com, kishon@ti.com, devicetree@vger.kernel.org, mark.rutland@arm.com, vivek.gautam@codeaurora.org, robh+dt@kernel.org, Jaehoon Chung Subject: [PATCH V3 4/4] PCI: exynos: support the using PHY generic framework Date: Mon, 13 Feb 2017 17:26:13 +0900 Message-id: <20170213082613.19628-5-jh80.chung@samsung.com> X-Mailer: git-send-email 2.10.2 In-reply-to: <20170213082613.19628-1-jh80.chung@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupik+LIzCtJLcpLzFFi42LZdlhTXXdF7sIIg+kvVS0ezNvGZrGkKcPi 5SFNi/lHzrFavHm7hsnixq82VosVX2ayW/Q/fs1sceFpD5vF+fMb2C0u75rDZnF23nE2ixnn 9zFZLL1+kcniyZRHrBaLtn5ht2jde4Td4sTPHcwOQh5r5q1h9Ljc18vksXPWXXaPBZtKPTat 6mTz2NIP5PVtWcXocfzGdiaPz5vkAjijUm0yUhNTUosUUvOS81My89JtlbyD453jTc0MDHUN LS3MlRTyEnNTbZVcfAJ03TJzgN5RUihLzCkFCgUkFhcr6dvZFOWXlqQqZOQXl9gqRRsaGukZ GpjrGRkZ6ZkYx1oZmQKVJKRmnLk1i7HghULFrvY1LA2MC6S7GDk5JARMJKZsus0KYYtJXLi3 nq2LkYtDSGApo8SM7T/YIZx2JokDBw6xwHQsa3jJCpFYzijRs3YeE4Tzg1Gia99/dpAqNgEd ie3fjjOB2CICshIfL+8Bm8sssJZZ4uPHTUAOB4ewgI/En1ZtkBoWAVWJJ5fusoHYvALWEn8u P2GE2CYvsfD8EbA5nAI2EpvmHwRbJiFwj13ixNFuRpA5EkALNh1ghqh3kdj+bhrUP8ISr45v YYewpSX+Lr3FCNHbzSjx78tGNginh1Hi1tbVTBBVxhL3H9wDm8QswCfR+/sJE8QCXomONiGI Eg+J3Q8mQpU7Skw8vQsaYP2MEtc2dbFPYJRZwMiwilEstaA4Nz212LTARK84Mbe4NC9dLzk/ dxMjOB1qRexg/Dcj6BCjAAejEg+vQMDCCCHWxLLiytxDjBIczEoivH8ygUK8KYmVValF+fFF pTmpxYcYTYEBNZFZSjQ5H5iq80riDU3MDE2MLIHQ3NBcSZw3ymBihJBAemJJanZqakFqEUwf EwenVANjuGLQljUyjUmf7l/pzk9bMe9j2OWPh66c1bssm8wgnlJU9VrXOGNZ74xDD95KX3r1 aWJV4LUtQoZRfddurNss+Xj2u+CcILejbz49LOu/tfBZnN5jPoatMUxadyJvL76Xuzhr0/pv SU/ms1W/P9iw+/DfzGv8bKsf8zJ9WaShYX11bR/n35f9oUosxRmJhlrMRcWJAHTmAemdAwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrKIsWRmVeSWpSXmKPExsVy+t9jAd3luQsjDLZ8t7J4MG8bm8WSpgyL l4c0LeYfOcdq8ebtGiaLG7/aWC1WfJnJbtH/+DWzxYWnPWwW589vYLe4vGsOm8XZecfZLGac 38dksfT6RSaLJ1MesVos2vqF3aJ17xF2ixM/dzA7CHmsmbeG0eNyXy+Tx85Zd9k9Fmwq9di0 qpPNY0s/kNe3ZRWjx/Eb25k8Pm+SC+CMcrPJSE1MSS1SSM1Lzk/JzEu3VQoNcdO1UFLIS8xN tVWK0PUNCVJSKEvMKQXyjAzQgINzgHuwkr5dglvGmVuzGAteKFTsal/D0sC4QLqLkZNDQsBE YlnDS1YIW0ziwr31bF2MXBxCAksZJWbsaWOEcH4wSry8B1HFJqAjsf3bcSYQW0RAVuLj5T1g HcwCq5kl9k45zNzFyMEhLOAj8adVG6SGRUBV4smlu2wgNq+AtcSfy08YIbbJSyw8fwRsDqeA jcSm+QfBbCGgmqOrZjNPYORdwMiwilEitSC5oDgpPdcoL7Vcrzgxt7g0L10vOT93EyM4yp5J 72A8vMv9EKMAB6MSD++P9wsihFgTy4orcw8xSnAwK4nw/slcGCHEm5JYWZValB9fVJqTWnyI 0RTosInMUqLJ+cAEkFcSb2hibmJubGBhbmlpYqQkzts4+1m4kEB6YklqdmpqQWoRTB8TB6dU A2NxxPQD0bEmHcXLTXIXZCuH/fPUTWlLnpXY7c/8pr9lzkz59ndHLm3Seiv+/xRLqOCHE4ZG jtlT+GoKnt8+ZF8kEPeq92TmnbZ6/oUnWE3C5Ezzd6ot0A62m/wxOnjCvAnf/q1YcVinopbh w2zNWe/kes6eWmKpferJXOHVMyT+bBQym/1uT5wSS3FGoqEWc1FxIgCafLkByAIAAA== X-MTR: 20000000000000000@CPGS X-CMS-MailID: 20170213082616epcas5p2a20cca498e9ddde7c5d3f7664fb8606e X-Msg-Generator: CA X-Sender-IP: 203.254.230.27 X-Local-Sender: =?UTF-8?B?7KCV7J6s7ZuIG1RpemVuIFBsYXRmb3JtIExhYihTL1fshLw=?= =?UTF-8?B?7YSwKRvsgrzshLHsoITsnpAbUzUo7LGF7J6EKS/ssYXsnoQ=?= X-Global-Sender: =?UTF-8?B?SmFlaG9vbiBDaHVuZxtUaXplbiBQbGF0Zm9ybSBMYWIuG1Nh?= =?UTF-8?B?bXN1bmcgRWxlY3Ryb25pY3MbUzUvU2VuaW9yIEVuZ2luZWVy?= X-Sender-Code: =?UTF-8?B?QzEwG1NUQUYbQzEwVjgxMTE=?= CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-HopCount: 7 X-CMS-RootMailID: 20170213082616epcas5p2a20cca498e9ddde7c5d3f7664fb8606e X-RootMTR: 20170213082616epcas5p2a20cca498e9ddde7c5d3f7664fb8606e References: <20170213082613.19628-1-jh80.chung@samsung.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Switch the pci-exynos driver to generic PHY framework. At the same time backward compatibility is preserved: Warning will be printed for old DTB. Refer to the binding file: - Documentation/devictree/bindings/pci/samsung,exynos5440-pcie.txt Signed-off-by: Jaehoon Chung Acked-by: Krzysztof Kozlowski Acked-by: Jingoo Han Reviewed-by: Pankaj Dubey Reviewed-by: Alim Akhtar Acked-by: Bjorn Helgaas --- Changelog on V3: - Changes the commit-message - Fixes the merge conflict Changelog on V2: - This patch is split from previous PATCH[1/4] - Maintain the backward compatibility - Adds 'using_phy' for cheching whether phy framework is used or not - Adds 'DEPRECATED' message for old dt-binding way drivers/pci/host/pci-exynos.c | 54 +++++++++++++++++++++++++++++++++++++++---- 1 file changed, 50 insertions(+), 4 deletions(-) diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c index 758906b..f6a8b6e 100644 --- a/drivers/pci/host/pci-exynos.c +++ b/drivers/pci/host/pci-exynos.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include #include @@ -110,6 +111,10 @@ struct exynos_pcie { struct exynos_pcie_clk_res *clk_res; const struct exynos_pcie_ops *ops; int reset_gpio; + + /* For Generic PHY Framework */ + bool using_phy; + struct phy *phy; }; struct exynos_pcie_ops { @@ -126,6 +131,10 @@ static int exynos5440_pcie_get_mem_resources(struct platform_device *pdev, struct resource *res; struct device *dev = ep->pp.dev; + /* If using the PHY framework, doesn't need to get other resource */ + if (ep->using_phy) + return 0; + ep->mem_res = devm_kzalloc(dev, sizeof(*ep->mem_res), GFP_KERNEL); if (!ep->mem_res) return -ENOMEM; @@ -396,10 +405,28 @@ static int exynos_pcie_establish_link(struct exynos_pcie *ep) } exynos_pcie_assert_core_reset(ep); - exynos_pcie_assert_phy_reset(ep); - exynos_pcie_deassert_phy_reset(ep); - exynos_pcie_power_on_phy(ep); - exynos_pcie_init_phy(ep); + + if (ep->using_phy) { + phy_reset(ep->phy); + + exynos_pcie_writel(ep->mem_res->elbi_base, 1, + PCIE_PWR_RESET); + + phy_power_on(ep->phy); + phy_init(ep->phy); + } else { + exynos_pcie_assert_phy_reset(ep); + exynos_pcie_deassert_phy_reset(ep); + exynos_pcie_power_on_phy(ep); + exynos_pcie_init_phy(ep); + + /* pulse for common reset */ + exynos_pcie_writel(ep->mem_res->block_base, 1, + PCIE_PHY_COMMON_RESET); + udelay(500); + exynos_pcie_writel(ep->mem_res->block_base, 0, + PCIE_PHY_COMMON_RESET); + } /* pulse for common reset */ exynos_pcie_writel(ep->mem_res->block_base, 1, PCIE_PHY_COMMON_RESET); @@ -418,6 +445,11 @@ static int exynos_pcie_establish_link(struct exynos_pcie *ep) if (!dw_pcie_wait_for_link(pp)) return 0; + if (ep->using_phy) { + phy_power_off(ep->phy); + return -ETIMEDOUT; + } + while (exynos_pcie_readl(ep->mem_res->phy_base, PCIE_PHY_PLL_LOCKED) == 0) { val = exynos_pcie_readl(ep->mem_res->block_base, @@ -624,6 +656,17 @@ static int __init exynos_pcie_probe(struct platform_device *pdev) ep->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0); + /* Assume that controller doesn't use the PHY framework */ + ep->using_phy = false; + + ep->phy = devm_of_phy_get(dev, np, NULL); + if (IS_ERR(ep->phy)) { + if (PTR_ERR(ep->phy) == -EPROBE_DEFER) + return PTR_ERR(ep->phy); + dev_warn(dev, "Use the 'phy' property. Current DT of pci-exynos was deprecated!!\n"); + } else + ep->using_phy = true; + if (ep->ops && ep->ops->get_mem_resources) { ret = ep->ops->get_mem_resources(pdev, ep); if (ret) @@ -647,6 +690,9 @@ static int __init exynos_pcie_probe(struct platform_device *pdev) return 0; fail_probe: + if (ep->using_phy) + phy_exit(ep->phy); + if (ep->ops && ep->ops->deinit_clk_resources) ep->ops->deinit_clk_resources(ep); return ret;