Message ID | 1673290621-22888-4-git-send-email-lizhi.hou@amd.com |
---|---|
State | New |
Headers | show
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Mon, 9 Jan 2023 12:57:09 -0600 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB05.amd.com (10.181.40.146) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Mon, 9 Jan 2023 12:57:09 -0600 Received: from xsjlizhih40.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2375.34 via Frontend Transport; Mon, 9 Jan 2023 12:57:08 -0600 From: Lizhi Hou <lizhi.hou@amd.com> To: <linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <robh@kernel.org>, <frowand.list@gmail.com>, <helgaas@kernel.org> CC: Lizhi Hou <lizhi.hou@amd.com>, <clement.leger@bootlin.com>, <max.zhen@amd.com>, <sonal.santan@amd.com>, <larry.liu@amd.com>, <brian.xu@amd.com>, <stefano.stabellini@xilinx.com>, <trix@redhat.com> Subject: [PATCH V6 3/3] PCI: Add PCI quirks to generate device tree node for Xilinx Alveo U50 Date: Mon, 9 Jan 2023 10:57:01 -0800 Message-ID: <1673290621-22888-4-git-send-email-lizhi.hou@amd.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1673290621-22888-1-git-send-email-lizhi.hou@amd.com> References: <1673290621-22888-1-git-send-email-lizhi.hou@amd.com> MIME-Version: 1.0 Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000C96C:EE_|SJ0PR12MB6903:EE_ X-MS-Office365-Filtering-Correlation-Id: b74b0686-2d38-4c8b-a006-08daf273500d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Series |
Generate device tree node for pci devices
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expand
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diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 285acc4aaccc..f184cf51b800 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -5992,3 +5992,14 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2d, dpc_log_size); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2f, dpc_log_size); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a31, dpc_log_size); #endif + +/* + * For PCI device which have multiple downstream devices, its driver may use + * a flattened device tree to describe the downstream devices. + * To overlay the flattened device tree, the PCI device and all its ancestor + * devices need to have device tree nodes on system base device tree. Thus, + * before driver probing, it might need to add a device tree node as the final + * fixup. + */ +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_XILINX, 0x5020, of_pci_make_dev_node); +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_XILINX, 0x5021, of_pci_make_dev_node);