Message ID | 1668044538-27334-4-git-send-email-lizhi.hou@amd.com |
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State | New |
Headers | show
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Wed, 9 Nov 2022 19:42:32 -0600 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB08.amd.com (10.181.40.132) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.31; Wed, 9 Nov 2022 17:42:31 -0800 Received: from xsjlizhih40.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2375.31 via Frontend Transport; Wed, 9 Nov 2022 19:42:30 -0600 From: Lizhi Hou <lizhi.hou@amd.com> To: <linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <robh@kernel.org>, <frowand.list@gmail.com>, <helgaas@kernel.org> CC: Lizhi Hou <lizhi.hou@amd.com>, <clement.leger@bootlin.com>, <max.zhen@amd.com>, <sonal.santan@amd.com>, <larry.liu@amd.com>, <brian.xu@amd.com>, <stefano.stabellini@xilinx.com>, <trix@redhat.com> Subject: [PATCH RFC V4 3/3] PCI: Add PCI quirks to generate device tree node for Xilinx Alveo U50 Date: Wed, 9 Nov 2022 17:42:18 -0800 Message-ID: <1668044538-27334-4-git-send-email-lizhi.hou@amd.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1668044538-27334-1-git-send-email-lizhi.hou@amd.com> References: <1668044538-27334-1-git-send-email-lizhi.hou@amd.com> MIME-Version: 1.0 Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT069:EE_|DM4PR12MB6304:EE_ X-MS-Office365-Filtering-Correlation-Id: 8fa28c46-b6c0-4624-099a-08dac2bcd873 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Generate device tree node for pci devices
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expand
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diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 4944798e75b5..5d76932f59ec 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -5956,3 +5956,14 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56b1, aspm_l1_acceptable_latency DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56c0, aspm_l1_acceptable_latency); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56c1, aspm_l1_acceptable_latency); #endif + +/* + * For PCI device which have multiple downstream devices, its driver may use + * a flattened device tree to describe the downstream devices. + * To overlay the flattened device tree, the PCI device and all its ancestor + * devices need to have device tree nodes on system base device tree. Thus, + * before driver probing, it might need to add a device tree node as the final + * fixup. + */ +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_XILINX, 0x5020, of_pci_make_dev_node); +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_XILINX, 0x5021, of_pci_make_dev_node);