| Message ID | 1581574091-240890-4-git-send-email-shawn.lin@rock-chips.com |
|---|---|
| State | New |
| Headers | show |
| Series | Add Rockchip new PCIe controller and combo phy support | expand |
On Thu, Feb 13, 2020 at 02:08:08PM +0800, Shawn Lin wrote: > On some platform, external MSI domain is using instead of the one > created by designware driver. For instance, if using GIC-V3-ITS > as a MSI domain, we only need set msi-map in the devicetree but > never need any bit in the designware driver to handle MSI stuff. > So skip allocating its own MSI domain for that case. A new field isn't needed. Just implement the msi_host_init() hook. Rob
diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 395feb8..e78d094 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -257,6 +257,10 @@ int dw_pcie_allocate_domains(struct pcie_port *pp) struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct fwnode_handle *fwnode = of_node_to_fwnode(pci->dev->of_node); + /* Rely on the external MSI domain */ + if (pp->msi_ext) + return 0; + pp->irq_domain = irq_domain_create_linear(fwnode, pp->num_vectors, &dw_pcie_msi_domain_ops, pp); if (!pp->irq_domain) { @@ -278,6 +282,9 @@ int dw_pcie_allocate_domains(struct pcie_port *pp) void dw_pcie_free_msi(struct pcie_port *pp) { + if (pp->msi_ext) + return; + if (pp->msi_irq) { irq_set_chained_handler(pp->msi_irq, NULL); irq_set_handler_data(pp->msi_irq, NULL); @@ -413,7 +420,8 @@ int dw_pcie_host_init(struct pcie_port *pp) if (ret) pci->num_viewport = 2; - if (pci_msi_enabled()) { + if (pci_msi_enabled() && + !pp->msi_ext) { /* * If a specific SoC driver needs to change the * default number of vectors, it needs to implement diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index a22ea59..eeafa52 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -201,6 +201,7 @@ struct pcie_port { u32 irq_mask[MAX_MSI_CTRLS]; struct pci_bus *root_bus; raw_spinlock_t lock; + int msi_ext; DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS); };
On some platform, external MSI domain is using instead of the one created by designware driver. For instance, if using GIC-V3-ITS as a MSI domain, we only need set msi-map in the devicetree but never need any bit in the designware driver to handle MSI stuff. So skip allocating its own MSI domain for that case. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> --- Changes in v2: None drivers/pci/controller/dwc/pcie-designware-host.c | 10 +++++++++- drivers/pci/controller/dwc/pcie-designware.h | 1 + 2 files changed, 10 insertions(+), 1 deletion(-)