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Tue, 28 Jan 2020 04:44:59 -0800 Received: from xsj-pvapsmtp01 (smtp.xilinx.com [149.199.38.66]) by xsj-smtp-dlp1.xlnx.xilinx.com (8.13.8/8.13.1) with ESMTP id 00SCiubw016809; Tue, 28 Jan 2020 04:44:56 -0800 Received: from [10.140.9.2] (helo=xhdbharatku40.xilinx.com) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1iwQEh-0006pq-Mk; Tue, 28 Jan 2020 04:44:56 -0800 From: Bharat Kumar Gogada To: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org Cc: bhelgaas@google.com, rgummal@xilinx.com, Bharat Kumar Gogada Subject: [PATCH v4 1/2] PCI: xilinx-cpm: Add device tree binding for Versal CPM host bridge. Date: Tue, 28 Jan 2020 18:14:42 +0530 Message-Id: <1580215483-8835-2-git-send-email-bharat.kumar.gogada@xilinx.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1580215483-8835-1-git-send-email-bharat.kumar.gogada@xilinx.com> References: <1580215483-8835-1-git-send-email-bharat.kumar.gogada@xilinx.com> X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.83; IPV:; CTRY:US; EFV:NLI; SFV:NSPM; SFS:(10009020)(4636009)(346002)(396003)(39860400002)(376002)(136003)(189003)(199004)(316002)(5660300002)(7696005)(70206006)(36756003)(70586007)(4326008)(107886003)(2906002)(26005)(356004)(6666004)(186003)(478600001)(426003)(2616005)(8936002)(9786002)(81166006)(81156014)(336012)(8676002); DIR:OUT; SFP:1101; SCL:1; SRVR:BL0PR02MB5394; H:xsj-pvapsmtpgw01; FPR:; SPF:Pass; LANG:en; PTR:unknown-60-83.xilinx.com; MX:1; A:1; MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 8cc6083f-bf2a-4629-dcf7-08d7a3efe65d X-MS-TrafficTypeDiagnostic: BL0PR02MB5394: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:4502; X-Forefront-PRVS: 029651C7A1 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: acwPlSjng19pLcdXUG/Hg7v5nYCd8XgMQW4qOMzzIbdEWA7lnpM8t/diGGyP0IdbA0w+zAF2CwDWUZuG/zFYz8F1Q8vAwTJn0/BokE+1SqqpJ40feBIjiht4QbDvXp51Lc2o7bR3lxLa6xD8C58S03wZFHKPEnOXR0DJqdFce4xb5rI1Ojw5oJpHXxxlQkun+EdYejNlgSj48s/DzCotyTPmu2veN8duthsHG1CAoFwsiy3FLsw4em2lzvAYame/qfeFPfn7qZIFWsYirPcyDIyZ2x6Ay1tyWo56wG9qgAuhwmCi4RJP7YVqBth4rVR+eVBvwSTcZwCkzP+O4IglctLodRIZhDyox3/6qD6w+eJsl8Xdbz5DWwtinpSGrU+v51oWj9qODjR1pVXkcAIBMtl6PuXpckA1zj1XfZ5MRG0D9VmbQw4cLqC0/PpNeewh X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Jan 2020 12:45:05.2165 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8cc6083f-bf2a-4629-dcf7-08d7a3efe65d X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.60.83]; Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL0PR02MB5394 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add device tree binding documentation for Versal CPM Root Port driver. Signed-off-by: Bharat Kumar Gogada --- .../devicetree/bindings/pci/xilinx-versal-cpm.txt | 66 ++++++++++++++++++++++ 1 file changed, 66 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/xilinx-versal-cpm.txt diff --git a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.txt b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.txt new file mode 100644 index 0000000..35f8556 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.txt @@ -0,0 +1,66 @@ +* Xilinx Versal CPM DMA Root Port Bridge DT description + +Required properties: +- #address-cells: Address representation for root ports, set to <3> +- #size-cells: Size representation for root ports, set to <2> +- #interrupt-cells: specifies the number of cells needed to encode an + interrupt source. The value must be 1. +- compatible: Should contain "xlnx,versal-cpm-host-1.00" +- reg: Should contain configuration space (includes bridge registers) and + CPM system level control and status registers, and length +- reg-names: Must include the following entries: + "cfg": configuration space region and bridge registers + "cpm_slcr": CPM system level control and status registers +- interrupts: Should contain AXI PCIe interrupt +- interrupt-map-mask, + interrupt-map: standard PCI properties to define the mapping of the + PCI interface to interrupt numbers. +- ranges: ranges for the PCI memory regions (I/O space region is not + supported by hardware) + Please refer to the standard PCI bus binding document for a more + detailed explanation +- msi-map: Maps a Requester ID to an MSI controller and associated MSI + sideband data +- interrupt-names: Must include the following entries: + "misc": interrupt asserted when legacy or error interrupt is received + +Interrupt controller child node ++++++++++++++++++++++++++++++++ +Required properties: +- interrupt-controller: identifies the node as an interrupt controller +- #address-cells: specifies the number of cells needed to encode an + address. The value must be 0. +- #interrupt-cells: specifies the number of cells needed to encode an + interrupt source. The value must be 1. + + +Refer to the following binding document for more detailed description on +the use of 'msi-map': + Documentation/devicetree/bindings/pci/pci-msi.txt + +Example: + pci@fca10000 { + #address-cells = <3>; + #interrupt-cells = <1>; + #size-cells = <2>; + compatible = "xlnx,versal-cpm-host-1.00"; + interrupt-map = <0 0 0 1 &pcie_intc_0 1>, + <0 0 0 2 &pcie_intc_0 2>, + <0 0 0 3 &pcie_intc_0 3>, + <0 0 0 4 &pcie_intc_0 4>; + interrupt-map-mask = <0 0 0 7>; + interrupt-parent = <&gic>; + interrupt-names = "misc"; + interrupts = <0 72 4>; + ranges = <0x02000000 0x00000000 0xE0000000 0x0 0xE0000000 0x00000000 0x10000000>, + <0x43000000 0x00000080 0x00000000 0x00000080 0x00000000 0x00000000 0x80000000>; + msi-map = <0x0 &its_gic 0x0 0x10000>; + reg = <0x6 0x00000000 0x0 0x1000000>, + <0x0 0xFCA10000 0x0 0x1000>; + reg-names = "cfg", "cpm_slcr"; + pcie_intc_0: pci-interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller ; + }; + };