From patchwork Thu Oct 8 19:54:16 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Daney X-Patchwork-Id: 527872 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 19BC5140E0F for ; Fri, 9 Oct 2015 06:54:25 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=q2UPwSIt; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754342AbbJHTyX (ORCPT ); Thu, 8 Oct 2015 15:54:23 -0400 Received: from mail-ig0-f177.google.com ([209.85.213.177]:35942 "EHLO mail-ig0-f177.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754203AbbJHTyW (ORCPT ); Thu, 8 Oct 2015 15:54:22 -0400 Received: by igcrk20 with SMTP id rk20so21061762igc.1; Thu, 08 Oct 2015 12:54:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=yAgCskF2g5GKNdiAAx2ET7Anf+TIXLVlX2HCcbj/KDg=; b=q2UPwSIt0BBkUqgIvDFHxfBNVCNRNuCuoVxHV9AQPCQFx/1EOgMii5sxQJ3JkmrcEC yEcWWVlMbbyjGaUYYGDr9qaSM97WurY3HhcxyvCQr2DU2+lUO1IIPa51luEdCbAcCDaV 8pG3YR+HW/eZLn5gobD6vSnMD0zas2mBOcLSAfS+cNGl2zhtthpy7EN6bpu7LkMS7D62 epWEBNLTNuBrxs9wfkm8kDenb/qgGu611sc1ukWIQlOcC2HzTMpYYc3hjghXgYiTmAUC TlyMk+jc7A5YfP+btp1YN5ny6/msYihL54JX+9IQpVOM//Wli+6nQKlQQes5r82Vqksn nFIw== X-Received: by 10.50.32.34 with SMTP id f2mr6036273igi.44.1444334061943; Thu, 08 Oct 2015 12:54:21 -0700 (PDT) Received: from dl.caveonetworks.com (64.2.3.194.ptr.us.xo.net. [64.2.3.194]) by smtp.gmail.com with ESMTPSA id 31sm17572207iom.35.2015.10.08.12.54.20 (version=TLSv1 cipher=RC4-SHA bits=128/128); Thu, 08 Oct 2015 12:54:20 -0700 (PDT) Received: from dl.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dl.caveonetworks.com (8.14.5/8.14.5) with ESMTP id t98JsIES004904; Thu, 8 Oct 2015 12:54:18 -0700 Received: (from ddaney@localhost) by dl.caveonetworks.com (8.14.5/8.14.5/Submit) id t98JsISx004903; Thu, 8 Oct 2015 12:54:18 -0700 From: David Daney To: linux-kernel@vger.kernel.org, Bjorn Helgaas , linux-pci@vger.kernel.org, Will Deacon , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Arnd Bergmann Cc: David Daney Subject: [PATCH] PCI: generic: Fix address window calculation for non-zero starting bus. Date: Thu, 8 Oct 2015 12:54:16 -0700 Message-Id: <1444334056-4870-1-git-send-email-ddaney.cavm@gmail.com> X-Mailer: git-send-email 1.7.11.7 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: David Daney Make the offset from the beginning of the "reg" property be from the starting bus number, rather than zero. Hoist the invariant size calculation out of the mapping for loop. Update host-generic-pci.txt to clarify the semantics of the "reg" property with respect to non-zero starting bus numbers. Signed-off-by: David Daney Reviewed-by: Arnd Bergmann Acked-by: Rob Herring --- This is a replacement for: https://lkml.org/lkml/2015/10/2/653 Since that patch is getting too much push-back, this is the only other option for fixing the driver to be internally consistent in its treatment of the offset from "reg" to the first bus in the "bus-range" property. Documentation/devicetree/bindings/pci/host-generic-pci.txt | 5 +++-- drivers/pci/host/pci-host-generic.c | 4 ++-- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/host-generic-pci.txt b/Documentation/devicetree/bindings/pci/host-generic-pci.txt index cf3e205..3f1d3fc 100644 --- a/Documentation/devicetree/bindings/pci/host-generic-pci.txt +++ b/Documentation/devicetree/bindings/pci/host-generic-pci.txt @@ -34,8 +34,9 @@ Properties of the host controller node: - #size-cells : Must be 2. - reg : The Configuration Space base address and size, as accessed - from the parent bus. - + from the parent bus. The base address corresponds to + the first bus in the "bus-range" property. If no + "bus-range" is specified, this will be bus 0 (the default). Properties of the /chosen node: diff --git a/drivers/pci/host/pci-host-generic.c b/drivers/pci/host/pci-host-generic.c index fe9a81b..bb93346 100644 --- a/drivers/pci/host/pci-host-generic.c +++ b/drivers/pci/host/pci-host-generic.c @@ -169,6 +169,7 @@ static int gen_pci_parse_map_cfg_windows(struct gen_pci *pci) struct resource *bus_range; struct device *dev = pci->host.dev.parent; struct device_node *np = dev->of_node; + u32 sz = 1 << pci->cfg.ops->bus_shift; err = of_address_to_resource(np, 0, &pci->cfg.res); if (err) { @@ -196,10 +197,9 @@ static int gen_pci_parse_map_cfg_windows(struct gen_pci *pci) bus_range = pci->cfg.bus_range; for (busn = bus_range->start; busn <= bus_range->end; ++busn) { u32 idx = busn - bus_range->start; - u32 sz = 1 << pci->cfg.ops->bus_shift; pci->cfg.win[idx] = devm_ioremap(dev, - pci->cfg.res.start + busn * sz, + pci->cfg.res.start + idx * sz, sz); if (!pci->cfg.win[idx]) return -ENOMEM;