From patchwork Fri Oct 2 18:44:02 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Daney X-Patchwork-Id: 525713 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 01727140D7E for ; Sat, 3 Oct 2015 04:47:00 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=kg8G8q7X; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754095AbbJBSqn (ORCPT ); Fri, 2 Oct 2015 14:46:43 -0400 Received: from mail-io0-f175.google.com ([209.85.223.175]:35602 "EHLO mail-io0-f175.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753481AbbJBSoP (ORCPT ); Fri, 2 Oct 2015 14:44:15 -0400 Received: by ioiz6 with SMTP id z6so129529091ioi.2; Fri, 02 Oct 2015 11:44:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=BhMw2ktZqLl9injS3HD8CxBLjNu/SuMkssZA8EuLaBc=; b=kg8G8q7XY5OuECvc1l3qDstxxqndqwqgr4/f04Qrh192UwvE4Uqarr/JdPAxLq/VTU 30kV9o6k3StSO0sVOTkvnps5E1dsjTVwB+hbtAYO77lZ9JIgP44UfuBvP/iIGy4/eSD5 0KEHdBgr+tr9INXrxNgJEOs93DDE2BuVNag4C8relgb2b7nZ7YaNXOMYDN58dlg+z9+N JX3ydf4GPfCEKNvj8c5PXka5vyYHYYBkqeWXovTZzpcLYfI58qW3KDAz9+EOwb0BqaBm /HCIYUY9LfxtHQ0/eapD3PxmkssSTNw0Vb690JjgMyKlkUM2oJlagyOa2IrTB5QrKKiY R8iQ== X-Received: by 10.107.15.27 with SMTP id x27mr18701624ioi.51.1443811454425; Fri, 02 Oct 2015 11:44:14 -0700 (PDT) Received: from dl.caveonetworks.com (64.2.3.194.ptr.us.xo.net. [64.2.3.194]) by smtp.gmail.com with ESMTPSA id 92sm5490760ioq.3.2015.10.02.11.44.08 (version=TLSv1 cipher=RC4-SHA bits=128/128); Fri, 02 Oct 2015 11:44:10 -0700 (PDT) Received: from dl.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dl.caveonetworks.com (8.14.5/8.14.5) with ESMTP id t92Ii7uC018934; Fri, 2 Oct 2015 11:44:07 -0700 Received: (from ddaney@localhost) by dl.caveonetworks.com (8.14.5/8.14.5/Submit) id t92Ii7ik018932; Fri, 2 Oct 2015 11:44:07 -0700 From: David Daney To: linux-kernel@vger.kernel.org, Bjorn Helgaas , linux-pci@vger.kernel.org, Will Deacon , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Marc Zyngier Cc: David Daney Subject: [PATCH v4 4/5] PCI: generic: Correct, and avoid overflow, in bus_max calculation. Date: Fri, 2 Oct 2015 11:44:02 -0700 Message-Id: <1443811443-18878-5-git-send-email-ddaney.cavm@gmail.com> X-Mailer: git-send-email 1.7.11.7 In-Reply-To: <1443811443-18878-1-git-send-email-ddaney.cavm@gmail.com> References: <1443811443-18878-1-git-send-email-ddaney.cavm@gmail.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: David Daney There are two problems with the bus_max calculation: 1) The u8 data type can overflow for large config space windows. 2) The calculation is incorrect for a bus range that doesn't start at zero. Since the configuration space is relative to bus zero, make bus_max just be the size of the config window scaled by bus_shift. Then clamp it to a maximum of 255, per PCI. Use a data type of int to avoid overflow problems. Update host-generic-pci.txt to clarify the semantics of the "reg" property with respect to non-zero starting bus numbers. Signed-off-by: David Daney --- Change from V3: Add to explanation of "reg" property in host-generic-pci.txt. Add error message if "reg" property is too big. Documentation/devicetree/bindings/pci/host-generic-pci.txt | 6 +++++- drivers/pci/host/pci-host-generic.c | 12 +++++++++--- 2 files changed, 14 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/host-generic-pci.txt b/Documentation/devicetree/bindings/pci/host-generic-pci.txt index cf3e205..42303bb 100644 --- a/Documentation/devicetree/bindings/pci/host-generic-pci.txt +++ b/Documentation/devicetree/bindings/pci/host-generic-pci.txt @@ -34,7 +34,11 @@ Properties of the host controller node: - #size-cells : Must be 2. - reg : The Configuration Space base address and size, as accessed - from the parent bus. + from the parent bus. The base address corresponds to + bus zero, even though the "bus-range" property may specify + a different starting bus number. The driver must only map + or access the portion of the Configuration Space that + corresponds to the "bus-range" Properties of the /chosen node: diff --git a/drivers/pci/host/pci-host-generic.c b/drivers/pci/host/pci-host-generic.c index 216ded5..5cce837 100644 --- a/drivers/pci/host/pci-host-generic.c +++ b/drivers/pci/host/pci-host-generic.c @@ -164,7 +164,7 @@ out_release_res: static int gen_pci_parse_map_cfg_windows(struct gen_pci *pci) { int err; - u8 bus_max; + int bus_max; resource_size_t busn; struct resource *bus_range; struct device *dev = pci->host.dev.parent; @@ -177,8 +177,14 @@ static int gen_pci_parse_map_cfg_windows(struct gen_pci *pci) } /* Limit the bus-range to fit within reg */ - bus_max = pci->cfg.bus_range->start + - (resource_size(&pci->cfg.res) >> pci->cfg.ops->bus_shift) - 1; + bus_max = (resource_size(&pci->cfg.res) >> pci->cfg.ops->bus_shift) - 1; + if (bus_max > 255) { + dev_err(dev, + "\"reg\" size corresponds to bus %d, truncating to 255\n", + bus_max); + bus_max = 255; + } + pci->cfg.bus_range->end = min_t(resource_size_t, pci->cfg.bus_range->end, bus_max);