From patchwork Thu Aug 20 13:58:33 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gabriele Paoloni X-Patchwork-Id: 509057 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 66D941402A3 for ; Thu, 20 Aug 2015 23:51:52 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751239AbbHTNvs (ORCPT ); Thu, 20 Aug 2015 09:51:48 -0400 Received: from szxga03-in.huawei.com ([119.145.14.66]:47887 "EHLO szxga03-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751203AbbHTNvr (ORCPT ); Thu, 20 Aug 2015 09:51:47 -0400 Received: from 172.24.1.51 (EHLO szxeml432-hub.china.huawei.com) ([172.24.1.51]) by szxrg03-dlp.huawei.com (MOS 4.4.3-GA FastPath queued) with ESMTP id BLJ78731; Thu, 20 Aug 2015 21:51:42 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by szxeml432-hub.china.huawei.com (10.82.67.209) with Microsoft SMTP Server id 14.3.235.1; Thu, 20 Aug 2015 21:51:34 +0800 From: Gabriele Paoloni To: , CC: , , , , , , , , Subject: [PATCH] PCI: designware: fix dw_pcie_cfg_write Date: Thu, 20 Aug 2015 21:58:33 +0800 Message-ID: <1440079113-165527-1-git-send-email-gabriele.paoloni@huawei.com> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020205.55D5DB6F.002A, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2013-05-26 15:14:31, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 7f61fc3c99e207d2b40b715f37657daa Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: gabriele paoloni Currently in dw_pcie_cfg_write() if the input size is 2 bytes the address offset is wrongly calculated as we mask also bit0 of "where" input parameter. Instead we should mask all bits of "where" except bit0 and bit1. Signed-off-by: Gabriele Paoloni --- drivers/pci/host/pcie-designware.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c index 69486be..a27f536 100644 --- a/drivers/pci/host/pcie-designware.c +++ b/drivers/pci/host/pcie-designware.c @@ -99,7 +99,7 @@ int dw_pcie_cfg_write(void __iomem *addr, int where, int size, u32 val) if (size == 4) writel(val, addr); else if (size == 2) - writew(val, addr + (where & 2)); + writew(val, addr + (where & 3)); else if (size == 1) writeb(val, addr + (where & 3)); else