From patchwork Mon Aug 17 11:06:18 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas Stach X-Patchwork-Id: 507941 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 0959F14012C for ; Mon, 17 Aug 2015 21:06:25 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754603AbbHQLGX (ORCPT ); Mon, 17 Aug 2015 07:06:23 -0400 Received: from metis.ext.pengutronix.de ([92.198.50.35]:44205 "EHLO metis.ext.pengutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754685AbbHQLGU (ORCPT ); Mon, 17 Aug 2015 07:06:20 -0400 Received: from dude.hi.4.pengutronix.de ([10.1.0.7] helo=dude.pengutronix.de.) by metis.ext.pengutronix.de with esmtp (Exim 4.80) (envelope-from ) id 1ZRIF9-0008IF-GQ; Mon, 17 Aug 2015 13:06:19 +0200 From: Lucas Stach To: Bjorn Helgaas , linux-pci@vger.kernel.org Cc: Jingoo Han , Pratyush Anand , patchwork-lst@pengutronix.de, kernel@pengutronix.de Subject: [PATCH v4 5/5] PCI: designware: set up high part of MSI target address Date: Mon, 17 Aug 2015 13:06:18 +0200 Message-Id: <1439809578-13654-6-git-send-email-l.stach@pengutronix.de> X-Mailer: git-send-email 2.4.6 In-Reply-To: <1439809578-13654-1-git-send-email-l.stach@pengutronix.de> References: <1439809578-13654-1-git-send-email-l.stach@pengutronix.de> X-SA-Exim-Connect-IP: 10.1.0.7 X-SA-Exim-Mail-From: l.stach@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-pci@vger.kernel.org Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Set up the high part of the MSI target address in order to allow the MSI target to reside above the 4GB mark on 64bit and PAE systems. Signed-off-by: Lucas Stach Acked-by: Pratyush Anand --- v4: fix target address setup in dw_pcie_msi_init() --- drivers/pci/host/pcie-designware.c | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c index 74034395cf2a..71629175d1a1 100644 --- a/drivers/pci/host/pcie-designware.c +++ b/drivers/pci/host/pcie-designware.c @@ -205,12 +205,16 @@ irqreturn_t dw_handle_msi_irq(struct pcie_port *pp) void dw_pcie_msi_init(struct pcie_port *pp) { + u64 msi_target; + pp->msi_data = __get_free_pages(GFP_KERNEL, 0); + msi_target = virt_to_phys((void *)pp->msi_data); /* program the msi_data */ dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4, - virt_to_phys((void *)pp->msi_data)); - dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4, 0); + (u32)(msi_target & 0xffffffff)); + dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4, + (u32)(msi_target >> 32 & 0xffffffff)); } static void dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq) @@ -299,12 +303,15 @@ no_valid_irq: static void dw_msi_setup_msg(struct pcie_port *pp, unsigned int irq, u32 pos) { struct msi_msg msg; + u64 msi_target; if (pp->ops->get_msi_addr) - msg.address_lo = pp->ops->get_msi_addr(pp); + msi_target = pp->ops->get_msi_addr(pp); else - msg.address_lo = virt_to_phys((void *)pp->msi_data); - msg.address_hi = 0x0; + msi_target = virt_to_phys((void *)pp->msi_data); + + msg.address_lo = (u32)(msi_target & 0xffffffff); + msg.address_hi = (u32)(msi_target >> 32 & 0xffffffff); if (pp->ops->get_msi_data) msg.data = pp->ops->get_msi_data(pp, pos);