From patchwork Mon Oct 20 02:19:11 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Zhu X-Patchwork-Id: 400952 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3059F14009E for ; Mon, 20 Oct 2014 13:51:52 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752013AbaJTCvh (ORCPT ); Sun, 19 Oct 2014 22:51:37 -0400 Received: from [157.56.111.119] ([157.56.111.119]:51168 "EHLO na01-bn1-obe.outbound.protection.outlook.com" rhost-flags-FAIL-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1752037AbaJTCvd (ORCPT ); Sun, 19 Oct 2014 22:51:33 -0400 Received: from DM2PR03CA0027.namprd03.prod.outlook.com (10.141.96.26) by BN3PR0301MB0852.namprd03.prod.outlook.com (25.160.154.15) with Microsoft SMTP Server (TLS) id 15.0.1054.13; Mon, 20 Oct 2014 02:49:40 +0000 Received: from BN1BFFO11FD048.protection.gbl (2a01:111:f400:7c10::1:136) by DM2PR03CA0027.outlook.office365.com (2a01:111:e400:2428::26) with Microsoft SMTP Server (TLS) id 15.0.1054.13 via Frontend Transport; Mon, 20 Oct 2014 02:49:40 +0000 Received: from az84smr01.freescale.net (192.88.158.2) by BN1BFFO11FD048.mail.protection.outlook.com (10.58.145.3) with Microsoft SMTP Server (TLS) id 15.0.1049.20 via Frontend Transport; Mon, 20 Oct 2014 02:49:39 +0000 Received: from shlinux1.ap.freescale.net (shlinux1.ap.freescale.net [10.192.225.216]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id s9K2nZ6L019776; Sun, 19 Oct 2014 19:49:38 -0700 Received: by shlinux1.ap.freescale.net (Postfix, from userid 1003) id 0C7341AE211; Mon, 20 Oct 2014 10:19:18 +0800 (CST) From: Richard Zhu To: CC: , , , , Richard Zhu , Richard Zhu Subject: [PATCH v7 08/13] PCI: imx6: Wait the clocks to stabilize after ref_en Date: Mon, 20 Oct 2014 10:19:11 +0800 Message-ID: <1413771556-32212-9-git-send-email-richard.zhu@freescale.com> X-Mailer: git-send-email 1.7.8 In-Reply-To: <1413771556-32212-1-git-send-email-richard.zhu@freescale.com> References: <1413771556-32212-1-git-send-email-richard.zhu@freescale.com> X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:192.88.158.2; CTRY:US; IPV:CAL; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(10019020)(6009001)(428002)(199003)(189002)(77096002)(50466002)(48376002)(99396003)(92726001)(92566001)(120916001)(33646002)(103686003)(97736003)(50986999)(76176999)(93916002)(62966002)(105586002)(2351001)(110136001)(4396001)(107046002)(50226001)(229853001)(101416001)(26826002)(81156004)(106466001)(20776003)(47776003)(42186005)(21056001)(64706001)(102836001)(88136002)(77156001)(87286001)(85306004)(6806004)(45336002)(19580405001)(19580395003)(36756003)(69596002)(46386002)(68736004)(44976005)(52956003)(31966008)(16796002)(89996001)(104166001)(95666004)(76482002)(87936001)(46102003)(84676001)(85852003)(80022003)(90966001); DIR:OUT; SFP:1102; SCL:1; SRVR:BN3PR0301MB0852; H:az84smr01.freescale.net; FPR:; MLV:ovrnspm; PTR:InfoDomainNonexistent; A:0; MX:1; LANG:en; MIME-Version: 1.0 X-Microsoft-Antispam: UriScan:; X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:;SRVR:BN3PR0301MB0852; X-Forefront-PRVS: 03706074BC Received-SPF: None (protection.outlook.com: shlinux1.ap.freescale.net does not designate permitted sender hosts) Authentication-Results: spf=none (sender IP is 192.88.158.2) smtp.mailfrom=r65037@shlinux1.ap.freescale.net; X-OriginatorOrg: freescale.com Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Richard Zhu For boards without a reset gpio we skip the delay between enabling the pcie_ref_clk and touching the RC registers for configuration. System would be hangs when the clocks are not yet settled in the DW PCIe core. So we need to make sure that there is always an appropriate delay between those two actions. Signed-off-by: Richard Zhu Tested-by: Tim Harvey --- drivers/pci/host/pci-imx6.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/pci/host/pci-imx6.c b/drivers/pci/host/pci-imx6.c index 233fe8a..eac96fb 100644 --- a/drivers/pci/host/pci-imx6.c +++ b/drivers/pci/host/pci-imx6.c @@ -275,15 +275,22 @@ static int imx6_pcie_deassert_core_reset(struct pcie_port *pp) goto err_pcie; } - /* allow the clocks to stabilize */ - usleep_range(200, 500); - /* power up core phy and enable ref clock */ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18); + /* + * the async reset input need ref clock to sync internally, + * when the ref clock comes after reset, internal synced + * reset time is too short , cannot meet the requirement. + * add one ~10us delay here. + */ + udelay(10); regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16); + /* allow the clocks to stabilize */ + usleep_range(200, 500); + /* Some boards don't have PCIe reset GPIO. */ if (gpio_is_valid(imx6_pcie->reset_gpio)) { gpio_set_value(imx6_pcie->reset_gpio, 0);