From patchwork Thu Oct 16 07:52:37 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Zhu X-Patchwork-Id: 400198 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id D02761400AB for ; Thu, 16 Oct 2014 19:23:23 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751033AbaJPIXU (ORCPT ); Thu, 16 Oct 2014 04:23:20 -0400 Received: from mail-bl2on0136.outbound.protection.outlook.com ([65.55.169.136]:20311 "EHLO na01-bl2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751269AbaJPIXK (ORCPT ); Thu, 16 Oct 2014 04:23:10 -0400 Received: from DM2PR0301MB0864.namprd03.prod.outlook.com (25.160.215.15) by DM2PR0301MB0893.namprd03.prod.outlook.com (25.160.216.143) with Microsoft SMTP Server (TLS) id 15.0.1049.19; Thu, 16 Oct 2014 08:23:08 +0000 Received: from CO2PR03CA0042.namprd03.prod.outlook.com (10.141.194.169) by DM2PR0301MB0864.namprd03.prod.outlook.com (25.160.215.15) with Microsoft SMTP Server (TLS) id 15.0.1049.19; Thu, 16 Oct 2014 08:23:07 +0000 Received: from BL2FFO11FD026.protection.gbl (2a01:111:f400:7c09::161) by CO2PR03CA0042.outlook.office365.com (2a01:111:e400:1414::41) with Microsoft SMTP Server (TLS) id 15.0.1054.13 via Frontend Transport; Thu, 16 Oct 2014 08:23:06 +0000 Received: from az84smr01.freescale.net (192.88.158.2) by BL2FFO11FD026.mail.protection.outlook.com (10.173.161.105) with Microsoft SMTP Server (TLS) id 15.0.1039.16 via Frontend Transport; Thu, 16 Oct 2014 08:23:05 +0000 Received: from shlinux1.ap.freescale.net (shlinux1.ap.freescale.net [10.192.225.216]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id s9G8N3Gs027327; Thu, 16 Oct 2014 01:23:04 -0700 Received: by shlinux1.ap.freescale.net (Postfix, from userid 1003) id 02CCD1AE20F; Thu, 16 Oct 2014 15:52:46 +0800 (CST) From: Richard Zhu To: CC: , , , , Richard Zhu , Richard Zhu Subject: [PATCH v6 07/13] ARM: imx6sx: Add imx6sx pcie related gpr bits definitions Date: Thu, 16 Oct 2014 15:52:37 +0800 Message-ID: <1413445963-24706-8-git-send-email-richard.zhu@freescale.com> X-Mailer: git-send-email 1.7.8 In-Reply-To: <1413445963-24706-1-git-send-email-richard.zhu@freescale.com> References: <1413445963-24706-1-git-send-email-richard.zhu@freescale.com> X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:192.88.158.2; CTRY:US; IPV:CAL; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(10019020)(6009001)(428002)(189002)(199003)(4396001)(84676001)(88136002)(50226001)(92726001)(89996001)(52956003)(46102003)(19580405001)(69596002)(85306004)(45336002)(120916001)(50986999)(99396003)(93916002)(76176999)(92566001)(19580395003)(21056001)(16796002)(76482002)(87286001)(97736003)(87936001)(6806004)(80022003)(68736004)(31966008)(26826002)(44976005)(47776003)(95666004)(107046002)(101416001)(20776003)(105586002)(62966002)(81156004)(36756003)(110136001)(42186005)(104166001)(102836001)(50466002)(85852003)(106466001)(46386002)(229853001)(103686003)(64706001)(77096002)(77156001)(2351001)(48376002)(33646002)(32563001)(90966001); DIR:OUT; SFP:1102; SCL:1; SRVR:DM2PR0301MB0864; H:az84smr01.freescale.net; FPR:; MLV:ovrnspm; PTR:InfoDomainNonexistent; MX:1; A:0; LANG:en; MIME-Version: 1.0 X-Microsoft-Antispam: UriScan:;UriScan:; X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:;SRVR:DM2PR0301MB0864; X-Forefront-PRVS: 036614DD9C Received-SPF: None (protection.outlook.com: shlinux1.ap.freescale.net does not designate permitted sender hosts) Authentication-Results: spf=none (sender IP is 192.88.158.2) smtp.mailfrom=r65037@shlinux1.ap.freescale.net; X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:;SRVR:DM2PR0301MB0893; X-OriginatorOrg: freescale.com Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Richard Zhu Signed-off-by: Richard Zhu --- include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h index ff44374..3273b87 100644 --- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h +++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h @@ -301,6 +301,7 @@ #define IMX6Q_GPR12_DEVICE_TYPE (0xf << 12) #define IMX6Q_GPR12_PCIE_CTL_2 BIT(10) #define IMX6Q_GPR12_LOS_LEVEL (0x1f << 4) +#define IMX6Q_GPR12_LOS_LEVEL_9 (0x9 << 4) #define IMX6Q_GPR13_SDMA_STOP_REQ BIT(30) #define IMX6Q_GPR13_CAN2_STOP_REQ BIT(29) @@ -395,4 +396,12 @@ #define IMX6SL_GPR1_FEC_CLOCK_MUX1_SEL_MASK (0x3 << 17) #define IMX6SL_GPR1_FEC_CLOCK_MUX2_SEL_MASK (0x1 << 14) +/* For imx6sx iomux gpr register field define */ +#define IMX6SX_GPR5_PCIE_BTNRST BIT(19) +#define IMX6SX_GPR5_PCIE_PERST BIT(18) + +#define IMX6SX_GPR12_PCIE_PM_TURN_OFF BIT(16) +#define IMX6SX_GPR12_PCIE_TEST_PD BIT(30) +#define IMX6SX_GPR12_RX_EQ_MASK (0x7 << 0) +#define IMX6SX_GPR12_RX_EQ_2 (0x2 << 0) #endif /* __LINUX_IMX6Q_IOMUXC_GPR_H */