From patchwork Fri Oct 10 05:41:10 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Zhu X-Patchwork-Id: 398458 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 5BC8914010F for ; Fri, 10 Oct 2014 17:11:50 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751433AbaJJGLr (ORCPT ); Fri, 10 Oct 2014 02:11:47 -0400 Received: from mail-bn1on0115.outbound.protection.outlook.com ([157.56.110.115]:21238 "EHLO na01-bn1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751292AbaJJGLp (ORCPT ); Fri, 10 Oct 2014 02:11:45 -0400 Received: from BN3PR0301CA0041.namprd03.prod.outlook.com (25.160.180.179) by BN3PR0301MB0852.namprd03.prod.outlook.com (25.160.154.15) with Microsoft SMTP Server (TLS) id 15.0.1049.19; Fri, 10 Oct 2014 06:11:42 +0000 Received: from BY2FFO11FD011.protection.gbl (2a01:111:f400:7c0c::152) by BN3PR0301CA0041.outlook.office365.com (2a01:111:e400:4000::51) with Microsoft SMTP Server (TLS) id 15.0.1049.19 via Frontend Transport; Fri, 10 Oct 2014 06:11:41 +0000 Received: from tx30smr01.am.freescale.net (192.88.168.50) by BY2FFO11FD011.mail.protection.outlook.com (10.1.14.129) with Microsoft SMTP Server (TLS) id 15.0.1039.16 via Frontend Transport; Fri, 10 Oct 2014 06:11:41 +0000 Received: from shlinux1.ap.freescale.net (shlinux1.ap.freescale.net [10.192.225.216]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id s9A6BbnP023632; Thu, 9 Oct 2014 23:11:39 -0700 Received: by shlinux1.ap.freescale.net (Postfix, from userid 1003) id 5B7E91AE208; Fri, 10 Oct 2014 13:41:17 +0800 (CST) From: Richard Zhu To: CC: , , , , Richard Zhu , Richard Zhu Subject: [PATCH v5 3/9] PCI: imx6: wait the clocks to stabilize after ref_en Date: Fri, 10 Oct 2014 13:41:10 +0800 Message-ID: <1412919676-25344-4-git-send-email-richard.zhu@freescale.com> X-Mailer: git-send-email 1.7.8 In-Reply-To: <1412919676-25344-1-git-send-email-richard.zhu@freescale.com> References: <1412919676-25344-1-git-send-email-richard.zhu@freescale.com> X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:192.88.168.50; CTRY:US; IPV:CAL; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(10019020)(6009001)(428002)(189002)(199003)(45336002)(44976005)(101416001)(120916001)(104166001)(107046002)(229853001)(2351001)(93916002)(26826002)(50466002)(76482002)(102836001)(31966008)(48376002)(50986999)(68736004)(92566001)(92726001)(19580395003)(16796002)(6806004)(95666004)(103686003)(76176999)(19580405001)(84676001)(87286001)(77096002)(88136002)(4396001)(50226001)(87936001)(106466001)(85852003)(42186005)(99396003)(52956003)(89996001)(33646002)(64706001)(105586002)(85306004)(46386002)(47776003)(20776003)(110136001)(36756003)(62966002)(46102003)(97736003)(77156001)(21056001)(80022003)(90966001); DIR:OUT; SFP:1102; SCL:1; SRVR:BN3PR0301MB0852; H:tx30smr01.am.freescale.net; FPR:; MLV:ovrnspm; PTR:InfoDomainNonexistent; MX:1; A:0; LANG:en; MIME-Version: 1.0 X-Microsoft-Antispam: UriScan:; X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:;SRVR:BN3PR0301MB0852; X-Forefront-PRVS: 03607C04F0 Received-SPF: None (protection.outlook.com: shlinux1.ap.freescale.net does not designate permitted sender hosts) Authentication-Results: spf=none (sender IP is 192.88.168.50) smtp.mailfrom=r65037@shlinux1.ap.freescale.net; X-OriginatorOrg: freescale.com Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Richard Zhu For boards without a reset gpio we skip the delay between enabling the pcie_ref_clk and touching the RC registers for configuration. System would be hangs when the clocks are not yet settled in the DW PCIe core. So we need to make sure that there is always an appropriate delay between those two actions. Signed-off-by: Richard Zhu Tested-by: Tim Harvey --- drivers/pci/host/pci-imx6.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/pci/host/pci-imx6.c b/drivers/pci/host/pci-imx6.c index 233fe8a..eac96fb 100644 --- a/drivers/pci/host/pci-imx6.c +++ b/drivers/pci/host/pci-imx6.c @@ -275,15 +275,22 @@ static int imx6_pcie_deassert_core_reset(struct pcie_port *pp) goto err_pcie; } - /* allow the clocks to stabilize */ - usleep_range(200, 500); - /* power up core phy and enable ref clock */ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18); + /* + * the async reset input need ref clock to sync internally, + * when the ref clock comes after reset, internal synced + * reset time is too short , cannot meet the requirement. + * add one ~10us delay here. + */ + udelay(10); regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16); + /* allow the clocks to stabilize */ + usleep_range(200, 500); + /* Some boards don't have PCIe reset GPIO. */ if (gpio_is_valid(imx6_pcie->reset_gpio)) { gpio_set_value(imx6_pcie->reset_gpio, 0);