From patchwork Fri Oct 10 05:41:08 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Zhu X-Patchwork-Id: 398457 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 0BF4D14010F for ; Fri, 10 Oct 2014 17:11:49 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751389AbaJJGLp (ORCPT ); Fri, 10 Oct 2014 02:11:45 -0400 Received: from mail-by2on0133.outbound.protection.outlook.com ([207.46.100.133]:45917 "EHLO na01-by2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1750905AbaJJGLp (ORCPT ); Fri, 10 Oct 2014 02:11:45 -0400 Received: from BL2PR03MB340.namprd03.prod.outlook.com (10.141.68.24) by BL2PR03MB260.namprd03.prod.outlook.com (10.255.231.27) with Microsoft SMTP Server (TLS) id 15.0.1049.19; Fri, 10 Oct 2014 06:11:43 +0000 Received: from BY2PR03CA076.namprd03.prod.outlook.com (10.141.249.49) by BL2PR03MB340.namprd03.prod.outlook.com (10.141.68.24) with Microsoft SMTP Server (TLS) id 15.0.1054.10; Fri, 10 Oct 2014 06:11:42 +0000 Received: from BY2FFO11FD036.protection.gbl (2a01:111:f400:7c0c::171) by BY2PR03CA076.outlook.office365.com (2a01:111:e400:2c5d::49) with Microsoft SMTP Server (TLS) id 15.0.1049.19 via Frontend Transport; Fri, 10 Oct 2014 06:11:41 +0000 Received: from tx30smr01.am.freescale.net (192.88.168.50) by BY2FFO11FD036.mail.protection.outlook.com (10.1.14.221) with Microsoft SMTP Server (TLS) id 15.0.1039.16 via Frontend Transport; Fri, 10 Oct 2014 06:11:41 +0000 Received: from shlinux1.ap.freescale.net (shlinux1.ap.freescale.net [10.192.225.216]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id s9A6BbJO023630; Thu, 9 Oct 2014 23:11:39 -0700 Received: by shlinux1.ap.freescale.net (Postfix, from userid 1003) id 4DF4C1AE205; Fri, 10 Oct 2014 13:41:17 +0800 (CST) From: Richard Zhu To: CC: , , , , Richard Zhu , Richard Zhu Subject: [PATCH v5 1/9] PCI: designware: refine setup_rc and add msi data restore Date: Fri, 10 Oct 2014 13:41:08 +0800 Message-ID: <1412919676-25344-2-git-send-email-richard.zhu@freescale.com> X-Mailer: git-send-email 1.7.8 In-Reply-To: <1412919676-25344-1-git-send-email-richard.zhu@freescale.com> References: <1412919676-25344-1-git-send-email-richard.zhu@freescale.com> X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:192.88.168.50; CTRY:US; IPV:CAL; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(10019020)(6009001)(428002)(189002)(199003)(21056001)(19580395003)(77156001)(19580405001)(104166001)(64706001)(20776003)(47776003)(6806004)(84676001)(80022003)(36756003)(44976005)(68736004)(46102003)(50986999)(76176999)(120916001)(76482002)(45336002)(46386002)(93916002)(92566001)(92726001)(101416001)(26826002)(102836001)(50466002)(48376002)(88136002)(87286001)(87936001)(85852003)(52956003)(62966002)(89996001)(99396003)(42186005)(97736003)(85306004)(77096002)(106466001)(50226001)(229853001)(4396001)(33646002)(2351001)(107046002)(95666004)(110136001)(16796002)(103686003)(31966008)(105586002)(90966001); DIR:OUT; SFP:1102; SCL:1; SRVR:BL2PR03MB340; H:tx30smr01.am.freescale.net; FPR:; MLV:ovrnspm; PTR:InfoDomainNonexistent; MX:1; A:0; LANG:en; MIME-Version: 1.0 X-Microsoft-Antispam: UriScan:;UriScan:; X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:;SRVR:BL2PR03MB340; X-Exchange-Antispam-Report-Test: UriScan:; X-Forefront-PRVS: 03607C04F0 Received-SPF: None (protection.outlook.com: shlinux1.ap.freescale.net does not designate permitted sender hosts) Authentication-Results: spf=none (sender IP is 192.88.168.50) smtp.mailfrom=r65037@shlinux1.ap.freescale.net; X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:;SRVR:BL2PR03MB260; X-OriginatorOrg: freescale.com Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Richard Zhu - move "program correct class for RC" from dw_pcie_host_init() to dw_pcie_setup_rc(). since this is RC setup, it's better to contained in dw_pcie_setup_rc function. Then, RC can be re-setup really by dw_pcie_setup_rc(). - add one re-store msi data function. Because that pcie controller maybe powered off during system suspend, and the msi data configuration would be lost. this functions can be used to restore the msi data during the resume callback. Signed-off-by: Richard Zhu --- drivers/pci/host/pcie-designware.c | 15 ++++++++++++--- drivers/pci/host/pcie-designware.h | 1 + 2 files changed, 13 insertions(+), 3 deletions(-) diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c index 538bbf3..ae1e6c5 100644 --- a/drivers/pci/host/pcie-designware.c +++ b/drivers/pci/host/pcie-designware.c @@ -194,6 +194,13 @@ void dw_pcie_msi_init(struct pcie_port *pp) dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4, 0); } +void dw_pcie_msi_cfg_restore(struct pcie_port *pp) +{ + dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4, + virt_to_phys((void *)pp->msi_data)); + dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4, 0); +} + static int find_valid_pos0(struct pcie_port *pp, int msgvec, int pos, int *pos0) { int flag = 1; @@ -570,9 +577,6 @@ int __init dw_pcie_host_init(struct pcie_port *pp) dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0); - /* program correct class for RC */ - dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI); - dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val); val |= PORT_LOGIC_SPEED_CHANGE; dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val); @@ -917,6 +921,11 @@ void dw_pcie_setup_rc(struct pcie_port *pp) val = memlimit | membase; dw_pcie_writel_rc(pp, val, PCI_MEMORY_BASE); + /* program correct class for RC */ + dw_pcie_readl_rc(pp, PCI_CLASS_REVISION, &val); + val |= PCI_CLASS_BRIDGE_PCI << 16; + dw_pcie_writel_rc(pp, val, PCI_CLASS_REVISION); + /* setup command register */ dw_pcie_readl_rc(pp, PCI_COMMAND, &val); val &= 0xffff0000; diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h index a476e60..bb75715 100644 --- a/drivers/pci/host/pcie-designware.h +++ b/drivers/pci/host/pcie-designware.h @@ -83,6 +83,7 @@ int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val); int dw_pcie_cfg_write(void __iomem *addr, int where, int size, u32 val); irqreturn_t dw_handle_msi_irq(struct pcie_port *pp); void dw_pcie_msi_init(struct pcie_port *pp); +void dw_pcie_msi_cfg_restore(struct pcie_port *pp); int dw_pcie_link_up(struct pcie_port *pp); void dw_pcie_setup_rc(struct pcie_port *pp); int dw_pcie_host_init(struct pcie_port *pp);