@@ -925,6 +925,8 @@ struct pci_bus *acpi_pci_root_create(struct acpi_pci_root *root,
host_bridge->native_pme = 0;
if (!(root->osc_control_set & OSC_PCI_EXPRESS_LTR_CONTROL))
host_bridge->native_ltr = 0;
+ }
+ if (!pcie_ports_native && !pcie_ports_dpc_native) {
if (!(root->osc_control_set & OSC_PCI_EXPRESS_DPC_CONTROL))
host_bridge->native_dpc = 0;
}
@@ -280,11 +280,12 @@ void pci_dpc_init(struct pci_dev *pdev)
static int dpc_probe(struct pcie_device *dev)
{
struct pci_dev *pdev = dev->port;
+ struct pci_host_bridge *host = pci_find_host_bridge(pdev->bus);
struct device *device = &dev->device;
int status;
u16 ctl, cap;
- if (!pcie_aer_is_native(pdev) && !pcie_ports_dpc_native)
+ if (!pcie_aer_is_native(pdev) && !host->native_dpc)
return -ENOTSUPP;
status = devm_request_threaded_irq(device, dev->irq, dpc_irq,
@@ -25,8 +25,6 @@
#define PCIE_PORT_DEVICE_MAXSERVICES 5
-extern bool pcie_ports_dpc_native;
-
#ifdef CONFIG_PCIEAER
int pcie_aer_init(void);
int pcie_aer_is_native(struct pci_dev *dev);
@@ -253,7 +253,7 @@ static int get_port_device_capability(struct pci_dev *dev)
*/
if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DPC) &&
pci_aer_available() &&
- (pcie_ports_dpc_native || (services & PCIE_PORT_SERVICE_AER)))
+ (host->native_dpc || (services & PCIE_PORT_SERVICE_AER)))
services |= PCIE_PORT_SERVICE_DPC;
if (pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM ||
@@ -1547,9 +1547,11 @@ static inline int pci_irqd_intx_xlate(struct irq_domain *d,
#ifdef CONFIG_PCIEPORTBUS
extern bool pcie_ports_disabled;
extern bool pcie_ports_native;
+extern bool pcie_ports_dpc_native;
#else
#define pcie_ports_disabled true
#define pcie_ports_native false
+#define pcie_ports_dpc_native false
#endif
#define PCIE_LINK_STATE_L0S BIT(0)