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[RESEND,v2,0/4] x86/PCI: Odd generic PIRQ router improvements

Message ID alpine.DEB.2.21.2203301527270.22465@angie.orcam.me.uk
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Series x86/PCI: Odd generic PIRQ router improvements | expand

Message

Maciej W. Rozycki March 31, 2022, 7:10 a.m. UTC 
Hi,

 This series was dropped from x86/irq due to a bug in a follow-up patch, 
so resending verbatim after re-verification.

 While working on the SiS85C497 PIRQ router I have noticed an odd
phenomenon with my venerable Tyan Tomcat IV S1564D board, where the PCI 
INTD# line of the USB host controller included as function 3 of the PIIX3 
southbridge cannot be routed in the `noapic' mode.  As it turns out the 
reason for this is the BIOS has two individual entries in its PIRQ table 
for two of its three functions, and the wrong one is chosen for routing 
said line.

 Strictly speaking this violates the PCI BIOS specification, but it can be 
easily worked around while preserving the semantics for compliant systems.

 Therefore I have come up with this patch series, which addresses this 
problem with 3/4, adds function reporting to the debug PIRQ table dump 
with 2/4 and also prints a usable physical memory address of the PIRQ 
table in a debug message with 1/4.

 Then 4/4 follows, addressing the inability to use a PIRQ table to route 
interrupts for devices placed behind PCI-to-PCI bridges on option cards, 
and especially where the BIOS has failed to enumerate the whole bus tree 
in the first place.

 See individual change descriptions for further details.

 Please apply.

  Maciej