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31 Jul 2024 07:41:22 -0700 X-CSE-ConnectionGUID: l35uENETTZuSqeYZKaJ8NQ== X-CSE-MsgGUID: IAgz6FMFQ++jt7b51wgCrA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,251,1716274800"; d="scan'208";a="55295528" Received: from test2-linux-lab.an.intel.com ([10.122.105.166]) by orviesa007.jf.intel.com with ESMTP; 31 Jul 2024 07:41:21 -0700 From: matthew.gerlach@linux.intel.com To: lpieralisi@kernel.org, kw@linux.com, robh@kernel.org, bhelgaas@google.com, krzk+dt@kernel.org, conor+dt@kernel.org, dinguyen@kernel.org, joyce.ooi@intel.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Matthew Gerlach Subject: [PATCH 0/7] Add PCIe Root Port support for Agilex family of chips Date: Wed, 31 Jul 2024 09:39:39 -0500 Message-Id: <20240731143946.3478057-1-matthew.gerlach@linux.intel.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Matthew Gerlach This patch set adds PCIe Root Port support for the Agilex family of FPGA chips. Patches 1 and 2 have been reviewed previously and individually on the mailing list and are included here with their revision history and Reviewed-by: tags for convenience and completeness. Patch 1: Convert text device tree binding for Altera Root Port PCIe controller to YAML. Patch 2: Convert text device tree binding for Altera PCIe MSI controller to YAML. Patch 3: Add new compatible strings for the three variants of the Agilex PCIe controller IP. Patch 4: Add a label to the soc@0 device tree node to be used by patch 5. Patch 5: Add base dtsi for PCIe Root Port support of the Agilex family of chips. Patch 6: Add dts enabling PCIe Root Port support on an Agilex F-series Development Kit. Patch 7: Update Altera PCIe controller driver to support the Agilex family of chips. D M, Sharath Kumar (1): pci: controller: pcie-altera: Add support for Agilex Matthew Gerlach (6): dt-bindings: PCI: altera: Convert to YAML dt-bindings: PCI: altera: msi: Convert to YAML dt-bindings: PCI: altera: Add binding for Agilex arm64: dts: agilex: add soc0 label arm64: dts: agilex: add dtsi for PCIe Root Port arm64: dts: agilex: add dts enabling PCIe Root Port .../bindings/pci/altera-pcie-msi.txt | 27 -- .../devicetree/bindings/pci/altera-pcie.txt | 50 ---- .../bindings/pci/altr,msi-controller.yaml | 65 +++++ .../bindings/pci/altr,pcie-root-port.yaml | 123 +++++++++ MAINTAINERS | 4 +- arch/arm64/boot/dts/intel/Makefile | 1 + arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 2 +- .../socfpga_agilex7f_socdk_pcie_root_port.dts | 16 ++ .../intel/socfpga_agilex_pcie_root_port.dtsi | 55 ++++ drivers/pci/controller/pcie-altera.c | 260 ++++++++++++++++-- 10 files changed, 507 insertions(+), 96 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pci/altera-pcie-msi.txt delete mode 100644 Documentation/devicetree/bindings/pci/altera-pcie.txt create mode 100644 Documentation/devicetree/bindings/pci/altr,msi-controller.yaml create mode 100644 Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex7f_socdk_pcie_root_port.dts create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex_pcie_root_port.dtsi