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Wed, 17 Jul 2024 20:55:20 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CY4PEPF0000EE3E.mail.protection.outlook.com (10.167.242.16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7784.11 via Frontend Transport; Wed, 17 Jul 2024 20:55:20 +0000 Received: from weiserver.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Wed, 17 Jul 2024 15:55:17 -0500 From: Wei Huang To: , , , CC: , , , , , , , , , , , , , , , , , , , Subject: [PATCH V3 00/10] PCIe TPH and cache direct injection support Date: Wed, 17 Jul 2024 15:55:01 -0500 Message-ID: <20240717205511.2541693-1-wei.huang2@amd.com> X-Mailer: git-send-email 2.45.1 Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE3E:EE_|SJ2PR12MB8805:EE_ X-MS-Office365-Filtering-Correlation-Id: 437752b0-a835-4b32-376c-08dca6a2c544 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|7416014|376014|1800799024|82310400026; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jul 2024 20:55:20.3012 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 437752b0-a835-4b32-376c-08dca6a2c544 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE3E.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB8805 Hi All, TPH (TLP Processing Hints) is a PCIe feature that allows endpoint devices to provide optimization hints for requests that target memory space. These hints, in a format called steering tag (ST), are provided in the requester's TLP headers and allow the system hardware, including the Root Complex, to optimize the utilization of platform resources for the requests. Upcoming AMD hardware implement a new Cache Injection feature that leverages TPH. Cache Injection allows PCIe endpoints to inject I/O Coherent DMA writes directly into an L2 within the CCX (core complex) closest to the CPU core that will consume it. This technology is aimed at applications requiring high performance and low latency, such as networking and storage applications. This series introduces generic TPH support in Linux, allowing STs to be retrieved from ACPI _DSM (as defined by ACPI) and used by PCIe endpoint drivers as needed. As a demonstration, it includes an example usage in the Broadcom BNXT driver. When running on Broadcom NICs with the appropriate firmware, Cache Injection shows substantial memory bandwidth savings and better network bandwidth using real-world benchmarks. This solution is vendor-neutral, as both TPH and ACPI _DSM are industry standards. V2->V3: * Rebase on top of pci/next tree (tag: pci-v6.11-changes) * Redefine PCI TPH registers (pci_regs.h) without breaking uapi * Fix commit subjects/messages for kernel options (Jonathan and Bjorn) * Break API functions into three individual patches for easy review * Rewrite lots of code in tph.c/tph.h based on feedback (Jonathan and Bjorn) V1->V2: * Rebase on top of pci.git/for-linus (6.10-rc1) * Address mismatched data types reported by Sparse (Sparse check passed) * Add a new API, pcie_tph_intr_vec_supported(), for checking IRQ mode support * Skip bnxt affinity notifier registration if pcie_tph_intr_vec_supported()=false * Minor fixes in bnxt driver (i.e. warning messages) Manoj Panicker (1): bnxt_en: Add TPH support in BNXT driver Michael Chan (1): bnxt_en: Pass NQ ID to the FW when allocating RX/RX AGG rings Wei Huang (8): PCI: Introduce PCIe TPH support framework PCI: Add TPH related register definition PCI/TPH: Add pci=notph to prevent use of TPH PCI/TPH: Add pci=nostmode to force No ST Mode PCI/TPH: Introduce API to check interrupt vector mode support PCI/TPH: Introduce API to retrieve TPH steering tags from ACPI PCI/TPH: Introduce API to update TPH steering tags in PCIe devices PCI/TPH: Add TPH documentation Documentation/PCI/index.rst | 1 + Documentation/PCI/tph.rst | 57 +++ .../admin-guide/kernel-parameters.txt | 2 + Documentation/driver-api/pci/pci.rst | 3 + drivers/net/ethernet/broadcom/bnxt/bnxt.c | 62 ++- drivers/net/ethernet/broadcom/bnxt/bnxt.h | 4 + drivers/pci/pci-driver.c | 12 +- drivers/pci/pci.c | 24 + drivers/pci/pci.h | 6 + drivers/pci/pcie/Kconfig | 11 + drivers/pci/pcie/Makefile | 1 + drivers/pci/pcie/tph.c | 443 ++++++++++++++++++ drivers/pci/probe.c | 1 + include/linux/pci-tph.h | 42 ++ include/linux/pci.h | 6 + include/uapi/linux/pci_regs.h | 28 +- 16 files changed, 696 insertions(+), 7 deletions(-) create mode 100644 Documentation/PCI/tph.rst create mode 100644 drivers/pci/pcie/tph.c create mode 100644 include/linux/pci-tph.h