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Tue, 25 Jun 2024 18:44:34 +0900 (KST) Received: from cheetah.sa.corp.samsungelectronics.net (unknown [107.109.115.53]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20240625094432epsmtip1b407f24481c763defe0216e4ea075f58~cNiDk1nS90463104631epsmtip1P; Tue, 25 Jun 2024 09:44:32 +0000 (GMT) From: Shradha Todi To: linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Cc: manivannan.sadhasivam@linaro.org, lpieralisi@kernel.org, kw@linux.com, robh@kernel.org, bhelgaas@google.com, jingoohan1@gmail.com, fancer.lancer@gmail.com, yoshihiro.shimoda.uh@renesas.com, conor.dooley@microchip.com, pankaj.dubey@samsung.com, gost.dev@samsung.com, Shradha Todi Subject: [PATCH v3 0/3] Add support for RAS DES feature in PCIe DW Date: Tue, 25 Jun 2024 15:08:10 +0530 Message-Id: <20240625093813.112555-1-shradha.t@samsung.com> X-Mailer: git-send-email 2.17.1 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupgk+LIzCtJLcpLzFFi42LZdlhTXZdpflWawbZJ3BZLmjIspmzawW6x oWMOq8XNAzuZLFZ8mclu0dDzm9Xi8q45bBZn5x1ns2j508Jicbelk9Vi0dYv7Bb/9wB19B6u tfi69zObA5/Hzll32T0WbCr12LSqk83jzrU9bB5Prkxn8rjzYymjx7czE1k8+rasYvT4vEku gDMq2yYjNTEltUghNS85PyUzL91WyTs43jne1MzAUNfQ0sJcSSEvMTfVVsnFJ0DXLTMH6HQl hbLEnFKgUEBicbGSvp1NUX5pSapCRn5xia1SakFKToFJgV5xYm5xaV66Xl5qiZWhgYGRKVBh QnbG4UtXWApuClT0XJ7L3MB4j7eLkZNDQsBE4sHdU0xdjFwcQgK7GSV+n+tghXA+MUrMvrIC KvONUWLTns0sMC3Pb8xkhEjsZZRoWrcaLCEk0Mok8Wu/N4jNJqAl0fi1ixnEFhGwljjcvoUN pIFZYBeTRM+Tc4wgCWEBJ4nza66wgtgsAqoSey8dYwKxeYEaru9uZYPYJi+xesMBZpBmCYGf 7BLPPt9gh0i4SHxYM50JwhaWeHV8C1RcSuLzu71QzekSKzfPYIawcyS+bV4CVW8vceDKHKCr OYAu0pRYv0sfIiwrMfXUOrASZgE+id7fT6DKeSV2zIOxlSW+/N0DDQlJiXnHLrNC2B4SHfu+ MUICIlbi+KHn7BMYZWchbFjAyLiKUTK1oDg3PbXYtMA4L7UcHlPJ+bmbGMFJUst7B+OjBx/0 DjEycTAeYpTgYFYS4Q0tqUoT4k1JrKxKLcqPLyrNSS0+xGgKDLOJzFKiyfnANJ1XEm9oYmlg YmZmZmJpbGaoJM77unVuipBAemJJanZqakFqEUwfEwenVAPTK5EL+x/4dWYYXX9+c930bFmJ M9VlimFhfDEcO06bqb7cJpao/DnDSbR9Q6uif1KyqwZb8bPFOlW+BfeaLk4IypgcrbzsOU/Q zZXMKjpvXe9+N/xg4Hy8dBd/vmtG3rOYsM/xvBrsgRd1tjJP3LdS9Y5vmPdO+afVt/JtjsUZ rHs+SfLtdan973YqVLUoFHj6Oi7WOzFN0mv6/XvCUUdkVl/LnZeld21CV+MRV/MbYmz7j33o bn0YtOv9W+n+B0wtLaZFmQ1lwqzXlXf6L7j94U9crN/tWd8YtthafdhUrr1l9dpvVZc+CDVW 8MSweV9eWaHbdNPhrJD2RgcHp4wze7OuB017w//O9bvhfyElluKMREMt5qLiRACFYd59GwQA AA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrCLMWRmVeSWpSXmKPExsWy7bCSnG7TxKo0g8PPdC2WNGVYTNm0g91i Q8ccVoubB3YyWaz4MpPdoqHnN6vF5V1z2CzOzjvOZtHyp4XF4m5LJ6vFoq1f2C3+7wHq6D1c a/F172c2Bz6PnbPusnss2FTqsWlVJ5vHnWt72DyeXJnO5HHnx1JGj29nJrJ49G1ZxejxeZNc AGcUl01Kak5mWWqRvl0CV8bhS1dYCm4KVPRcnsvcwHiPt4uRk0NCwETi+Y2ZjF2MXBxCArsZ JQ5MesUIkZCU+HxxHROELSyx8t9zdoiiZiaJQ393sYAk2AS0JBq/djGD2CICthL3H01mBSli FjjBJHF78gZWkISwgJPE+TVXwGwWAVWJvZeOgU3lFbCWuL67lQ1ig7zE6g0HmCcw8ixgZFjF KJlaUJybnltsWGCUl1quV5yYW1yal66XnJ+7iREcsFpaOxj3rPqgd4iRiYPxEKMEB7OSCG9o SVWaEG9KYmVValF+fFFpTmrxIUZpDhYlcd5vr3tThATSE0tSs1NTC1KLYLJMHJxSDUwT1ANF Uw+2dLt+EHsh1vK2Mj77wnXxVyVV3eeZDidN3tsY/VvKoHz+yulLNY3vTn91+f2iHVEFV+p0 xdisJZRkXk11vn9+7fZfv/9O7tDbkcqR2KCseYM7sav2gVZSWVT0ttgVH388fbDTZYKy04lV 3+xnBzF6qpx8F7zn6lqD4k3NB9827nfYfHdS85buziqJWCVJLqM+NSdNsVkH+ZpmiPeVvZjn Nm2tRJbV54mSh3/q7GLOmXg671V1I1P99LrLqtKH7M+/TOdu7PUPUr436dxzJt6YFjaOWtvj 1UsUT2R//qrRVCVgntImZf13hm1cm31iytprmx0vrWo8cT+s2Vzw/MGia6m1FRV1DkosxRmJ hlrMRcWJAE3gMqTHAgAA X-CMS-MailID: 20240625094434epcas5p2e48bda118809ccb841c983d737d4f09d X-Msg-Generator: CA X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20240625094434epcas5p2e48bda118809ccb841c983d737d4f09d References: Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: DesignWare controller provides a vendor specific extended capability called RASDES as an IP feature. This extended capability provides hardware information like: - Debug registers to know the state of the link or controller. - Error injection mechanisms to inject various PCIe errors including sequence number, CRC - Statistical counters to know how many times a particular event occurred However, in Linux we do not have any generic or custom support to be able to use this feature in an efficient manner. This is the reason we are proposing this framework. Debug and bring up time of high-speed IPs are highly dependent on costlier hardware analyzers and this solution will in some ways help to reduce the HW analyzer usage. The debugfs entries can be used to get information about underlying hardware and can be shared with user space. Separate debugfs entries has been created to cater to all the DES hooks provided by the controller. The debugfs entries interacts with the RASDES registers in the required sequence and provides the meaningful data to the user. This eases the effort to understand and use the register information for debugging. v2: https://lore.kernel.org/lkml/20240319163315.GD3297@thinkpad/T/ v1: https://lore.kernel.org/all/20210518174618.42089-1-shradha.t@samsung.com/T/ Shradha Todi (3): PCI: dwc: Add support for vendor specific capability search PCI: debugfs: Add support for RASDES framework in DWC PCI: dwc: Create debugfs files in DWC driver drivers/pci/controller/dwc/Kconfig | 8 + drivers/pci/controller/dwc/Makefile | 1 + .../controller/dwc/pcie-designware-debugfs.c | 474 ++++++++++++++++++ .../controller/dwc/pcie-designware-debugfs.h | 0 .../pci/controller/dwc/pcie-designware-host.c | 2 + drivers/pci/controller/dwc/pcie-designware.c | 20 + drivers/pci/controller/dwc/pcie-designware.h | 18 + 7 files changed, 523 insertions(+) create mode 100644 drivers/pci/controller/dwc/pcie-designware-debugfs.c create mode 100644 drivers/pci/controller/dwc/pcie-designware-debugfs.h