From patchwork Wed Jul 6 10:43:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pali_Roh=C3=A1r?= X-Patchwork-Id: 1652919 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20201202 header.b=nh8cmyXU; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4LdGNj3l2mz9sGg for ; Wed, 6 Jul 2022 20:43:33 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232876AbiGFKna (ORCPT ); Wed, 6 Jul 2022 06:43:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56828 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232324AbiGFKn3 (ORCPT ); Wed, 6 Jul 2022 06:43:29 -0400 Received: from sin.source.kernel.org (sin.source.kernel.org [145.40.73.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1EEF1B6F; Wed, 6 Jul 2022 03:43:23 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sin.source.kernel.org (Postfix) with ESMTPS id 4B838CE1EBC; Wed, 6 Jul 2022 10:43:22 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 452CDC3411C; Wed, 6 Jul 2022 10:43:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1657104200; bh=ZJU7+A8sh/C/YCWpWSHDj402O/F82gQIyYiqc8Vq+qE=; h=From:To:Cc:Subject:Date:From; b=nh8cmyXUfOvYI6WT/AqaEO7/btmBNWEvYeHfvCxNxPIErrpWyhHpKR+fhDtiBlvfa kT8ArZVV+1VD/6vlI01haiBNIlM+IlQtrAb/N+NaUp7z93wJLoENFaSD3my3yn0tS4 wMDuaZjjAlgQ5ROrTtALTzAF0Up4SJbomsO3rV4MVqdNQyCAOWd1wD1FYRlvNbTvUw ydBkCWCUX67FXFmcmfwJ/lcrXbeEDhV9s7IxPHyhwMhgdb0IGACmK27xw9oNsNdbMV If7giLMUEZpHlF1AReLsG27w2cYIcAr+1bDlGCJD8k46sn0/tXu5mq3V0+KBw4JBbJ KJyiIeWlt7FYQ== Received: by pali.im (Postfix) id 41DC57BA; Wed, 6 Jul 2022 12:43:17 +0200 (CEST) From: =?utf-8?q?Pali_Roh=C3=A1r?= To: Michael Ellerman , Benjamin Herrenschmidt , Paul Mackerras , Christophe Leroy , =?utf-8?q?C=C3=A9dric_Le_Go?= =?utf-8?q?ater?= , Nick Child , Bjorn Helgaas Cc: linuxppc-dev@lists.ozlabs.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 0/5] powerpc/pci: Cleanup unused code and enable 256 PCI buses Date: Wed, 6 Jul 2022 12:43:03 +0200 Message-Id: <20220706104308.5390-1-pali@kernel.org> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 X-Spam-Status: No, score=-7.8 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org This patch series cleanup unused code by eliminating it at compile time and then enable usage of all 256 PCI buses per every PCI domain as currently PCI bus numbers have to be unique across all PCI domains. So first bus number of each PCI domain would be zero and not the bus number of the previous domain plus one. As such bus assignment changes BDF address of every PCI device on multi-domain system, this new "feature" is configurable by config option to prevent regressions. Tested on Freescale P2020 board. Before this patch lspci reports: 8000:00:00.0 PCI bridge: Freescale Semiconductor Inc P2020E (rev 21) 8000:01:00.0 USB controller: Texas Instruments TUSB73x0 SuperSpeed USB 3.0 xHCI Host Controller (rev 02) 9000:02:00.0 PCI bridge: Freescale Semiconductor Inc P2020E (rev 21) 9000:03:00.0 Network controller: Qualcomm Atheros AR93xx Wireless Network Adapter (rev 01) a000:04:00.0 PCI bridge: Freescale Semiconductor Inc P2020E (rev 21) a000:05:00.0 Network controller: Qualcomm Atheros QCA986x/988x 802.11ac Wireless Network Adapter With these patches and enabled config option it reports: 8000:00:00.0 PCI bridge: Freescale Semiconductor Inc P2020E (rev 21) 8000:01:00.0 USB controller: Texas Instruments TUSB73x0 SuperSpeed USB 3.0 xHCI Host Controller (rev 02) 9000:00:00.0 PCI bridge: Freescale Semiconductor Inc P2020E (rev 21) 9000:01:00.0 Network controller: Qualcomm Atheros AR93xx Wireless Network Adapter (rev 01) a000:00:00.0 PCI bridge: Freescale Semiconductor Inc P2020E (rev 21) a000:01:00.0 Network controller: Qualcomm Atheros QCA986x/988x 802.11ac Wireless Network Adapter Now every PCIe Root Port is on bus zero and theoretically with enough multiport PCIe switches connected to every PCIe Root Port, it should be possible to have 256 PCI buses on every PCIe controller (as each is in own PCI domain) and therefore connect more PCIe cards as without these patches. Pali Rohár (5): powerpc/pci: Hide pci_device_from_OF_node() for non-powermac code powerpc/pci: Make pcibios_make_OF_bus_map() static powerpc/pci: Hide pci_create_OF_bus_map() for non-chrp code powerpc/pci: Disable filling pci-OF-bus-map for non-chrp/powermac powerpc/pci: Add config option for using all 256 PCI buses arch/powerpc/Kconfig | 11 +++++++++++ arch/powerpc/include/asm/pci-bridge.h | 4 ++++ arch/powerpc/kernel/pci_32.c | 27 +++++++++++++++++++++------ arch/powerpc/kernel/pci_64.c | 2 ++ 4 files changed, 38 insertions(+), 6 deletions(-)