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[v5,0/2] pciutils: Add basic decode support for CXL DVSEC

Message ID 20200415004751.2103963-1-sean.v.kelley@linux.intel.com
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Series pciutils: Add basic decode support for CXL DVSEC | expand

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Sean V Kelley April 15, 2020, 12:47 a.m. UTC 
Changes since v4 [1]:

- Describe CXL in terms of both the DVSEC Vendor ID and DVSEC ID.
(Bjorn Helgaas)

- Check the DVSEC Vendor ID first. Both the DVSEC Vendor ID and DVSEC ID must
match for CXL identification.
(Bjorn Helgaas)

- Renamed is_flexbus_cap() to is_cxl_cap() to more accurately reflect use.

- Added descriptions to the CXL support/control/status register bitfields.

[1] https://lore.kernel.org/linux-pci/20200413153526.805776-1-sean.v.kelley@linux.intel.com/

This patch series adds support for basic lspci decode of Compute eXpress Link[2],
a new CPU interconnect building upon PCIe. As a foundation for the CXL
support it adds separate Designated Vendor-Specific Capability (DVSEC) defines
and a cap function so as to align with PCIe r5.0, sec 7.9.6.2 terms and
provide available details. It makes use of the DVSEC Vendor ID and DVSEC ID so as
to identify a CXL capable device.

[2] https://www.computeexpresslink.org/

Sean V Kelley (2):
  pciutils: Decode available DVSEC details
  pciutils: Decode Compute eXpress Link DVSEC

 lib/header.h        |  24 ++++
 ls-ecaps.c          |  79 +++++++++-
 tests/cap-dvsec     | 340 ++++++++++++++++++++++++++++++++++++++++++++
 tests/cap-dvsec-cxl | 340 ++++++++++++++++++++++++++++++++++++++++++++
 4 files changed, 782 insertions(+), 1 deletion(-)
 create mode 100644 tests/cap-dvsec
 create mode 100644 tests/cap-dvsec-cxl

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2.26.0