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[106.168.128.197]) by smtp.gmail.com with ESMTPSA id 17-20020aa79211000000b00662610cf7a8sm6723376pfo.172.2023.06.12.03.04.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Jun 2023 03:04:41 -0700 (PDT) From: tkuw584924@gmail.com X-Google-Original-From: Takahiro.Kuwano@infineon.com To: linux-mtd@lists.infradead.org Cc: tudor.ambarus@linaro.org, pratyush@kernel.org, michael@walle.cc, miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com, d-gole@ti.com, tkuw584924@gmail.com, Bacem.Daassi@infineon.com, Takahiro Kuwano Subject: [PATCH 3/5] mtd: spi-nor: spansion: Add MCP support in octal_dtr_enable() Date: Mon, 12 Jun 2023 19:04:07 +0900 Message-Id: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230612_030442_968445_DD04D07B X-CRM114-Status: GOOD ( 16.17 ) X-Spam-Score: 0.1 (/) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: From: Takahiro Kuwano S28HS02GT is multi-chip package (MCP) device that requires Octal DTR configuraion for each die. We can access to configuration registers in each die by using params->n_dice and params->vreg_offset[] p [...] Content analysis details: (0.1 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:429 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider [tkuw584924[at]gmail.com] 0.2 FREEMAIL_ENVFROM_END_DIGIT Envelope-from freemail username ends in digit [tkuw584924[at]gmail.com] -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-mtd" Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org From: Takahiro Kuwano S28HS02GT is multi-chip package (MCP) device that requires Octal DTR configuraion for each die. We can access to configuration registers in each die by using params->n_dice and params->vreg_offset[] populated from SFDP. Signed-off-by: Takahiro Kuwano --- drivers/mtd/spi-nor/spansion.c | 71 +++++++++++++++++++++++++--------- 1 file changed, 53 insertions(+), 18 deletions(-) diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c index 0daa3a357ae8..eda3731c17be 100644 --- a/drivers/mtd/spi-nor/spansion.c +++ b/drivers/mtd/spi-nor/spansion.c @@ -156,7 +156,7 @@ static int cypress_nor_sr_ready_and_clear(struct spi_nor *nor) return 1; } -static int cypress_nor_setup_memlat(struct spi_nor *nor) +static int cypress_nor_setup_memlat(struct spi_nor *nor, u64 addr) { struct spi_mem_op op; u8 *buf = nor->bouncebuf; @@ -164,8 +164,7 @@ static int cypress_nor_setup_memlat(struct spi_nor *nor) u8 addr_mode_nbytes = nor->params->addr_mode_nbytes; op = (struct spi_mem_op) - CYPRESS_NOR_RD_ANY_REG_OP(addr_mode_nbytes, - SPINOR_REG_CYPRESS_CFR2V, 0, buf); + CYPRESS_NOR_RD_ANY_REG_OP(addr_mode_nbytes, addr, 0, buf); ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto); if (ret) @@ -175,13 +174,12 @@ static int cypress_nor_setup_memlat(struct spi_nor *nor) *buf &= ~SPINOR_REG_CYPRESS_CFR2_MEMLAT_MASK; *buf |= SPINOR_REG_CYPRESS_CFR2_MEMLAT_11_24; op = (struct spi_mem_op) - CYPRESS_NOR_WR_ANY_REG_OP(addr_mode_nbytes, - SPINOR_REG_CYPRESS_CFR2V, 1, buf); + CYPRESS_NOR_WR_ANY_REG_OP(addr_mode_nbytes, addr, 1, buf); return spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto); } -static int cypress_nor_setup_opiddr(struct spi_nor *nor, bool enable) +static int cypress_nor_setup_opiddr(struct spi_nor *nor, u64 addr, bool enable) { struct spi_mem_op op; u8 *buf = nor->bouncebuf; @@ -191,8 +189,7 @@ static int cypress_nor_setup_opiddr(struct spi_nor *nor, bool enable) buf[0] = SPINOR_REG_CYPRESS_CFR5_OCT_DTR_EN; op = (struct spi_mem_op) CYPRESS_NOR_WR_ANY_REG_OP(nor->params->addr_mode_nbytes, - SPINOR_REG_CYPRESS_CFR5V, 1, - buf); + addr, 1, buf); } else { /* * The register is 1-byte wide, but 1-byte transactions are not @@ -203,8 +200,7 @@ static int cypress_nor_setup_opiddr(struct spi_nor *nor, bool enable) buf[0] = SPINOR_REG_CYPRESS_CFR5_OCT_DTR_DS; buf[1] = 0; op = (struct spi_mem_op) - CYPRESS_NOR_WR_ANY_REG_OP(nor->addr_nbytes, - SPINOR_REG_CYPRESS_CFR5V, 2, + CYPRESS_NOR_WR_ANY_REG_OP(nor->addr_nbytes, addr, 2, buf); } @@ -600,6 +596,49 @@ static struct spi_nor_fixups s25hx_t_fixups = { .late_init = s25hx_t_late_init, }; +static int cypress_nor_octal_dtr_enable_single_chip(struct spi_nor *nor, + bool enable) +{ + int ret; + + if (enable) { + ret = cypress_nor_setup_memlat(nor, SPINOR_REG_CYPRESS_CFR2V); + if (ret) + return ret; + + nor->read_dummy = 24; + } + + return cypress_nor_setup_opiddr(nor, SPINOR_REG_CYPRESS_CFR5V, enable); +} + +static int cypress_nor_octal_dtr_enable_mcp(struct spi_nor *nor, bool enable) +{ + struct spi_nor_flash_parameter *params = nor->params; + u64 addr; + u8 i; + int ret; + + if (enable) { + for (i = 0; i < params->n_dice; i++) { + addr = params->vreg_offset[i] + SPINOR_REG_CYPRESS_CFR2; + ret = cypress_nor_setup_memlat(nor, addr); + if (ret) + return ret; + } + nor->read_dummy = 24; + } + + for (i = 0; i < params->n_dice; i++) { + addr = params->vreg_offset[i] + SPINOR_REG_CYPRESS_CFR5; + ret = cypress_nor_setup_opiddr(nor, addr, enable); + if (ret) + return ret; + } + + return 0; +} + /** * cypress_nor_octal_dtr_enable() - Enable octal DTR on Cypress flashes. * @nor: pointer to a 'struct spi_nor' @@ -616,15 +655,11 @@ static int cypress_nor_octal_dtr_enable(struct spi_nor *nor, bool enable) u8 naddr, ndummy; enum spi_nor_protocol proto; - if (enable) { - ret = cypress_nor_setup_memlat(nor); - if (ret) - return ret; - - nor->read_dummy = 24; - } + if (nor->params->n_dice) + ret = cypress_nor_octal_dtr_enable_mcp(nor, enable); + else + ret = cypress_nor_octal_dtr_enable_single_chip(nor, enable); - ret = cypress_nor_setup_opiddr(nor, enable); if (ret) return ret;