From patchwork Wed Mar 7 11:31:05 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vipin Kumar X-Patchwork-Id: 145202 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from merlin.infradead.org (merlin.infradead.org [IPv6:2001:4978:20e::2]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 3D14EB6EF1 for ; Wed, 7 Mar 2012 22:35:54 +1100 (EST) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1S5F8m-00089t-IS; Wed, 07 Mar 2012 11:34:45 +0000 Received: from eu1sys200aog106.obsmtp.com ([207.126.144.121]) by merlin.infradead.org with smtps (Exim 4.76 #1 (Red Hat Linux)) id 1S5F6X-0006gU-LO for linux-mtd@lists.infradead.org; Wed, 07 Mar 2012 11:32:27 +0000 Received: from beta.dmz-ap.st.com ([138.198.100.35]) (using TLSv1) by eu1sys200aob106.postini.com ([207.126.147.11]) with SMTP ID DSNKT1dHQ9Psm8hyUJ5/9rXnoOgw+5PX0WL0@postini.com; Wed, 07 Mar 2012 11:32:24 UTC Received: from zeta.dmz-ap.st.com (ns6.st.com [138.198.234.13]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 022FDB8; Wed, 7 Mar 2012 11:23:51 +0000 (GMT) Received: from Webmail-ap.st.com (eapex1hubcas2.st.com [10.80.176.10]) by zeta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 0EBD1130D; Wed, 7 Mar 2012 11:32:17 +0000 (GMT) Received: from localhost (10.199.82.178) by Webmail-ap.st.com (10.80.176.7) with Microsoft SMTP Server (TLS) id 8.3.192.1; Wed, 7 Mar 2012 19:31:48 +0800 From: Vipin Kumar To: Subject: [PATCH 17/18] fsmc/nand: Access the NAND device word by word whenever possible Date: Wed, 7 Mar 2012 17:01:05 +0530 Message-ID: X-Mailer: git-send-email 1.7.0.4 In-Reply-To: References: MIME-Version: 1.0 X-Spam-Note: CRM114 invocation failed X-Spam-Score: -4.2 (----) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-4.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [207.126.144.121 listed in list.dnswl.org] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Vipin Kumar , Artem.Bityutskiy@nokia.com, linus.walleij@linaro.org X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-mtd-bounces@lists.infradead.org Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org The default way of accessing nand device is using the nand width. This means that 8bit devices are using u8 * and 16bit devices are accessed using u16 *. This results in a non-optimal performance since the FSMC is designed to translate the normal word accesses into device width based accesses. This patch implements read_buf and write_buf callbacks using word by word accesses. Signed-off-by: Vipin Kumar Reviewed-by: Viresh Kumar --- drivers/mtd/nand/fsmc_nand.c | 55 ++++++++++++++++++++++++++++++++++++++++++ include/linux/mtd/fsmc.h | 6 ++++ 2 files changed, 61 insertions(+), 0 deletions(-) diff --git a/drivers/mtd/nand/fsmc_nand.c b/drivers/mtd/nand/fsmc_nand.c index 1f00b37..3828279 100644 --- a/drivers/mtd/nand/fsmc_nand.c +++ b/drivers/mtd/nand/fsmc_nand.c @@ -692,6 +692,52 @@ static int count_written_bits(uint8_t *buff, int size, int max_bits) } /* + * fsmc_write_buf - write buffer to chip + * @mtd: MTD device structure + * @buf: data buffer + * @len: number of bytes to write + */ +static void fsmc_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) +{ + int i; + struct nand_chip *chip = mtd->priv; + + if (IS_ALIGNED((uint32_t)buf, sizeof(uint32_t)) && + IS_ALIGNED(len, sizeof(uint32_t))) { + uint32_t *p = (uint32_t *)buf; + len = len >> 2; + for (i = 0; i < len; i++) + writel(p[i], chip->IO_ADDR_W); + } else { + for (i = 0; i < len; i++) + writeb(buf[i], chip->IO_ADDR_W); + } +} + +/* + * fsmc_read_buf - read chip data into buffer + * @mtd: MTD device structure + * @buf: buffer to store date + * @len: number of bytes to read + */ +static void fsmc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) +{ + int i; + struct nand_chip *chip = mtd->priv; + + if (IS_ALIGNED((uint32_t)buf, sizeof(uint32_t)) && + IS_ALIGNED(len, sizeof(uint32_t))) { + uint32_t *p = (uint32_t *)buf; + len = len >> 2; + for (i = 0; i < len; i++) + p[i] = readl(chip->IO_ADDR_R); + } else { + for (i = 0; i < len; i++) + buf[i] = readb(chip->IO_ADDR_R); + } +} + +/* * fsmc_read_page_hwecc * @mtd: mtd info structure * @chip: nand chip info structure @@ -993,6 +1039,15 @@ static int __init fsmc_nand_probe(struct platform_device *pdev) if (pdata->width == FSMC_NAND_BW16) nand->options |= NAND_BUSWIDTH_16; + /* + * use customized (word by word) version of read_buf, write_buf if + * access_with_dev_width is reset supported + */ + if (pdata->mode == USE_WORD_ACCESS) { + nand->read_buf = fsmc_read_buf; + nand->write_buf = fsmc_write_buf; + } + fsmc_nand_setup(regs, host->bank, nand->options & NAND_BUSWIDTH_16, host->dev_timings); diff --git a/include/linux/mtd/fsmc.h b/include/linux/mtd/fsmc.h index c4ac07a..1edd2b3 100644 --- a/include/linux/mtd/fsmc.h +++ b/include/linux/mtd/fsmc.h @@ -141,6 +141,11 @@ struct fsmc_nand_timings { uint8_t tset; }; +enum access_mode { + USE_DMA_ACCESS = 1, + USE_WORD_ACCESS, +}; + /** * fsmc_nand_platform_data - platform specific NAND controller config * @partitions: partition table for the platform, use a default fallback @@ -164,6 +169,7 @@ struct fsmc_nand_platform_data { /* CLE, ALE offsets */ unsigned long cle_off; unsigned long ale_off; + enum access_mode mode; void (*select_bank)(uint32_t bank, uint32_t busw); };