| Message ID | 20240722084952.608770-1-linchengming884@gmail.com |
|---|---|
| State | New |
| Headers | show |
| Series | [v2] mtd: spi-nor: macronix: Add support for serial NOR flash | expand |
On Mon Jul 22, 2024 at 10:49 AM CEST, Cheng Ming Lin wrote: > From: Cheng Ming Lin <chengminglin@mxic.com.tw> > > MX66U1G45G and MX66L2G45G are Macronix serial NOR flash. > > These flashes have been tested on Xilinx Zynq-picozed board > using MXIC SPI controller. I've asked for a changelog. Now, what you've sent is a v2 (of what seems to be a split off of a split off). Before sending out another version, please carefully read: https://www.kernel.org/doc/html/latest/process/submitting-patches.html To be clear, please explain why this is a split off of the larger series, what has changed (or if nothing has changed then state so). Why did you split it even more (before it were two patches). Honestly, back when Jaime submitted these patches, I already spent way too much time to review this stuff just to get it dropped or handed over to another employee who then comes back very late. Please align your workflow at Macronix and get an internal review and some training how to submit patches upstream and don't put that burden on maintainers. Thanks, -michael
Hi, Michael Walle <mwalle@kernel.org> 於 2024年7月22日 週一 下午5:20寫道： > > On Mon Jul 22, 2024 at 10:49 AM CEST, Cheng Ming Lin wrote: > > From: Cheng Ming Lin <chengminglin@mxic.com.tw> > > > > MX66U1G45G and MX66L2G45G are Macronix serial NOR flash. > > > > These flashes have been tested on Xilinx Zynq-picozed board > > using MXIC SPI controller. > > I've asked for a changelog. Now, what you've sent is a v2 (of what > seems to be a split off of a split off). Before sending out another > version, please carefully read: > https://www.kernel.org/doc/html/latest/process/submitting-patches.html > I apologize for the misunderstanding. The lack of a changelog is my oversight. > To be clear, please explain why this is a split off of the larger > series, what has changed (or if nothing has changed then state so). > Why did you split it even more (before it were two patches). > The patch Jaime previously submitted included support for octal DTR mode and added the new octal NOR flash ID with RWW feature. However, these two things should belong to different patch series, so I split them apart. The reason for splitting them again this time is because I think that adding support for the octal NOR flash with RWW feature should be proposed after Alvinzhou's v9 version, which supports octal DTR mode, is accepted. So, I independently added support for serial NOR flash without RWW feature. > Honestly, back when Jaime submitted these patches, I already spent > way too much time to review this stuff just to get it dropped or > handed over to another employee who then comes back very late. > Please align your workflow at Macronix and get an internal review > and some training how to submit patches upstream and don't put that > burden on maintainers. > I apologize again for adding burden to the maintainers. Moving forward, we will ensure everything is internally reviewed before submitting patches. Thank you for your patience in addressing this matter. > Thanks, > -michael Best regards, Cheng Ming Lin
diff --git a/drivers/mtd/spi-nor/macronix.c b/drivers/mtd/spi-nor/macronix.c index ea6be95e75a5..387836b27605 100644 --- a/drivers/mtd/spi-nor/macronix.c +++ b/drivers/mtd/spi-nor/macronix.c @@ -90,6 +90,10 @@ static const struct flash_info macronix_nor_parts[] = { .name = "mx66l1g45g", .size = SZ_128M, .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, + }, { + .id = SNOR_ID(0xc2, 0x20, 0x1c), + .size = SZ_256M, + .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, }, { .id = SNOR_ID(0xc2, 0x23, 0x14), .name = "mx25v8035f", @@ -143,6 +147,11 @@ static const struct flash_info macronix_nor_parts[] = { .size = SZ_64M, .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, .fixup_flags = SPI_NOR_4B_OPCODES, + }, { + .id = SNOR_ID(0xc2, 0x25, 0x3b), + .size = SZ_128M, + .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, + .fixup_flags = SPI_NOR_4B_OPCODES, }, { .id = SNOR_ID(0xc2, 0x25, 0x3c), .name = "mx66u2g45g",