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[211.75.127.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1fc0bc392a7sm86526905ad.230.2024.07.18.00.55.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Jul 2024 00:55:12 -0700 (PDT) Received: from hqs-appsw-a2o.mp600.macronix.com (linux-patcher [172.17.236.67]) by twhmp6px (Postfix) with ESMTPS id F2151805EF; Thu, 18 Jul 2024 16:04:23 +0800 (CST) From: Cheng Ming Lin To: miquel.raynal@bootlin.com, vigneshr@ti.com, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org Cc: richard@nod.at, alvinzhou@mxic.com.tw, leoyu@mxic.com.tw, Cheng Ming Lin Subject: [PATCH v2 2/2] mtd: spinand: macronix: Fixups for Plane Select bit Date: Thu, 18 Jul 2024 15:53:56 +0800 Message-Id: <20240718075356.488253-3-linchengming884@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240718075356.488253-1-linchengming884@gmail.com> References: <20240718075356.488253-1-linchengming884@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240718_005514_021309_441131D0 X-CRM114-Status: GOOD ( 11.39 ) X-Spam-Score: -1.8 (-) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: From: Cheng Ming Lin Macronix serial NAND flash with a two-plane structure requires insertion of Plane Select bit into the column address during the write_to_cache operation. Additionally, for MX35{U,F}2G14AC, insertion of Plane Select bit into the column address is required during the read_from_cache operation. Content analysis details: (-1.8 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:534 listed in] [list.dnswl.org] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider [linchengming884(at)gmail.com] 0.2 FREEMAIL_ENVFROM_END_DIGIT Envelope-from freemail username ends in digit [linchengming884(at)gmail.com] X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-mtd" Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org From: Cheng Ming Lin Macronix serial NAND flash with a two-plane structure requires insertion of Plane Select bit into the column address during the write_to_cache operation. Additionally, for MX35{U,F}2G14AC, insertion of Plane Select bit into the column address is required during the read_from_cache operation. Signed-off-by: Cheng Ming Lin --- drivers/mtd/nand/spi/macronix.c | 66 ++++++++++++++++++++++++++++++--- 1 file changed, 60 insertions(+), 6 deletions(-) diff --git a/drivers/mtd/nand/spi/macronix.c b/drivers/mtd/nand/spi/macronix.c index 3f9e9c572854..eda67091edc0 100644 --- a/drivers/mtd/nand/spi/macronix.c +++ b/drivers/mtd/nand/spi/macronix.c @@ -100,6 +100,54 @@ static int mx35lf1ge4ab_ecc_get_status(struct spinand_device *spinand, return -EINVAL; } +/** + * write_plane_select_bit_in_cadd - Write Plane Select bit to the column address + * @spinand: SPI NAND device + * @req: NAND I/O request object + * @column: the column address + * + * Macronix serial NAND flash with a two-plane structure + * should insert Plane Select bit into the column address + * during the write_to_cache operation. + * + * Return: the column address after insertion of Plane Select bit + */ +static unsigned int write_plane_select_bit_in_cadd(struct spinand_device *spinand, + const struct nand_page_io_req *req, unsigned int column) +{ + struct nand_device *nand = spinand_to_nand(spinand); + + return column | (req->pos.plane << fls(nanddev_page_size(nand))); +} + +/** + * read_plane_select_bit_in_cadd - Write Plane Select bit to the column address + * @spinand: SPI NAND device + * @req: NAND I/O request object + * @column: the column address + * + * MX35{U,F}2G14AC also need to insert Plane Select bit + * into the column address during the read_from_cache operation. + * + * Return: the column address after insertion of Plane Select bit + */ +static u16 read_plane_select_bit_in_cadd(struct spinand_device *spinand, + const struct nand_page_io_req *req, u16 column) +{ + struct nand_device *nand = spinand_to_nand(spinand); + + return column | (req->pos.plane << fls(nanddev_page_size(nand))); +} + +static const struct spi_nand_fixups write_fixups = { + .write_to_cache = write_plane_select_bit_in_cadd, +}; + +static const struct spi_nand_fixups read_and_write_fixups = { + .write_to_cache = write_plane_select_bit_in_cadd, + .read_from_cache = read_plane_select_bit_in_cadd, +}; + static const struct spinand_info macronix_spinand_table[] = { SPINAND_INFO("MX35LF1GE4AB", SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x12), @@ -157,7 +205,8 @@ static const struct spinand_info macronix_spinand_table[] = { &write_cache_variants, &update_cache_variants), SPINAND_HAS_QE_BIT, - SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL)), + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL), + SPINAND_PLANE_SELECT_BIT(&write_fixups)), SPINAND_INFO("MX35LF2G24AD-Z4I8", SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x64, 0x03), NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), @@ -175,7 +224,8 @@ static const struct spinand_info macronix_spinand_table[] = { &write_cache_variants, &update_cache_variants), SPINAND_HAS_QE_BIT, - SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL)), + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL), + SPINAND_PLANE_SELECT_BIT(&write_fixups)), SPINAND_INFO("MX35LF4G24AD-Z4I8", SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x75, 0x03), NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1), @@ -215,7 +265,8 @@ static const struct spinand_info macronix_spinand_table[] = { &update_cache_variants), SPINAND_HAS_QE_BIT, SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, - mx35lf1ge4ab_ecc_get_status)), + mx35lf1ge4ab_ecc_get_status), + SPINAND_PLANE_SELECT_BIT(&read_and_write_fixups)), SPINAND_INFO("MX35UF4G24AD", SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xb5, 0x03), NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 2, 1, 1), @@ -225,7 +276,8 @@ static const struct spinand_info macronix_spinand_table[] = { &update_cache_variants), SPINAND_HAS_QE_BIT, SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, - mx35lf1ge4ab_ecc_get_status)), + mx35lf1ge4ab_ecc_get_status), + SPINAND_PLANE_SELECT_BIT(&write_fixups)), SPINAND_INFO("MX35UF4G24AD-Z4I8", SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xf5, 0x03), NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1), @@ -255,7 +307,8 @@ static const struct spinand_info macronix_spinand_table[] = { &update_cache_variants), SPINAND_HAS_QE_BIT, SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, - mx35lf1ge4ab_ecc_get_status)), + mx35lf1ge4ab_ecc_get_status), + SPINAND_PLANE_SELECT_BIT(&read_and_write_fixups)), SPINAND_INFO("MX35UF2G24AD", SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xa4, 0x03), NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 2, 1, 1), @@ -265,7 +318,8 @@ static const struct spinand_info macronix_spinand_table[] = { &update_cache_variants), SPINAND_HAS_QE_BIT, SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, - mx35lf1ge4ab_ecc_get_status)), + mx35lf1ge4ab_ecc_get_status), + SPINAND_PLANE_SELECT_BIT(&write_fixups)), SPINAND_INFO("MX35UF2G24AD-Z4I8", SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xe4, 0x03), NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),