@@ -124,6 +124,7 @@ xe-y += xe_bb.o \
xe_ring_ops.o \
xe_sa.o \
xe_sched_job.o \
+ xe_spi.o \
xe_step.o \
xe_sync.o \
xe_tile.o \
@@ -35,6 +35,7 @@
#include "xe_pcode.h"
#include "xe_pm.h"
#include "xe_query.h"
+#include "xe_spi.h"
#include "xe_tile.h"
#include "xe_ttm_stolen_mgr.h"
#include "xe_ttm_sys_mgr.h"
@@ -515,6 +516,7 @@ int xe_device_probe(struct xe_device *xe)
goto err_irq_shutdown;
}
+ xe_spi_init(xe);
xe_heci_gsc_init(xe);
err = xe_display_init(xe);
@@ -562,6 +564,7 @@ void xe_device_remove(struct xe_device *xe)
xe_display_fini(xe);
xe_heci_gsc_fini(xe);
+ xe_spi_fini(xe);
xe_irq_shutdown(xe);
}
@@ -12,6 +12,8 @@
#include <drm/drm_file.h>
#include <drm/ttm/ttm_device.h>
+#include <linux/intel_dg_spi_aux.h>
+
#include "xe_devcoredump_types.h"
#include "xe_heci_gsc.h"
#include "xe_gt_types.h"
@@ -432,6 +434,9 @@ struct xe_device {
/** @heci_gsc: graphics security controller */
struct xe_heci_gsc heci_gsc;
+ /** @spi: discrete graphics spi */
+ struct intel_dg_spi_dev spi;
+
/** @needs_flr_on_fini: requests function-reset on fini */
bool needs_flr_on_fini;
new file mode 100644
@@ -0,0 +1,78 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2019-2024, Intel Corporation. All rights reserved.
+ */
+
+#include <linux/intel_dg_spi_aux.h>
+#include <linux/pci.h>
+#include "xe_device_types.h"
+#include "xe_spi.h"
+
+#define GEN12_GUNIT_SPI_BASE 0x00102040
+#define GEN12_GUNIT_SPI_SIZE 0x80
+#define HECI_FW_STATUS_2_SPI_ACCESS_MODE BIT(3)
+
+static const struct intel_dg_spi_region regions[INTEL_DG_SPI_REGIONS] = {
+ [0] = { .name = "DESCRIPTOR", },
+ [2] = { .name = "GSC", },
+ [11] = { .name = "OptionROM", },
+ [12] = { .name = "DAM", },
+};
+
+static void xe_spi_release_dev(struct device *dev)
+{
+}
+
+void xe_spi_init(struct xe_device *xe)
+{
+ struct intel_dg_spi_dev *spi = &xe->spi;
+ struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
+ struct auxiliary_device *aux_dev = &spi->aux_dev;
+ int ret;
+
+ /* Only the DGFX devices have internal SPI */
+ if (!IS_DGFX(xe))
+ return;
+
+ spi->writeable_override = false;
+ spi->bar.parent = &pdev->resource[0];
+ spi->bar.start = GEN12_GUNIT_SPI_BASE + pdev->resource[0].start;
+ spi->bar.end = spi->bar.start + GEN12_GUNIT_SPI_SIZE - 1;
+ spi->bar.flags = IORESOURCE_MEM;
+ spi->bar.desc = IORES_DESC_NONE;
+ spi->regions = regions;
+
+ aux_dev->name = "spi";
+ aux_dev->id = (pci_domain_nr(pdev->bus) << 16) |
+ PCI_DEVID(pdev->bus->number, pdev->devfn);
+ aux_dev->dev.parent = &pdev->dev;
+ aux_dev->dev.release = xe_spi_release_dev;
+
+ ret = auxiliary_device_init(aux_dev);
+ if (ret) {
+ dev_err(&pdev->dev, "xe-spi aux init failed %d\n", ret);
+ return;
+ }
+
+ ret = auxiliary_device_add(aux_dev);
+ if (ret) {
+ dev_err(&pdev->dev, "xe-spi aux add failed %d\n", ret);
+ auxiliary_device_uninit(aux_dev);
+ return;
+ }
+}
+
+void xe_spi_fini(struct xe_device *xe)
+{
+ struct intel_dg_spi_dev *spi = &xe->spi;
+ struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
+
+ /* Only the DGFX devices have internal SPI */
+ if (!IS_DGFX(xe))
+ return;
+
+ dev_dbg(&pdev->dev, "removing xe-spi cell\n");
+
+ auxiliary_device_delete(&spi->aux_dev);
+ auxiliary_device_uninit(&spi->aux_dev);
+}
new file mode 100644
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2019-2024 Intel Corporation. All rights reserved.
+ */
+
+#ifndef __XE_SPI_H__
+#define __XE_SPI_H__
+
+struct xe_device;
+
+void xe_spi_init(struct xe_device *xe);
+
+void xe_spi_fini(struct xe_device *xe);
+
+#endif /* __XE_SPI_H__ */
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com> --- drivers/gpu/drm/xe/Makefile | 1 + drivers/gpu/drm/xe/xe_device.c | 3 ++ drivers/gpu/drm/xe/xe_device_types.h | 5 ++ drivers/gpu/drm/xe/xe_spi.c | 78 ++++++++++++++++++++++++++++ drivers/gpu/drm/xe/xe_spi.h | 15 ++++++ 5 files changed, 102 insertions(+) create mode 100644 drivers/gpu/drm/xe/xe_spi.c create mode 100644 drivers/gpu/drm/xe/xe_spi.h