| Message ID | 20240215134856.1313239-5-quic_mdalam@quicinc.com |
|---|---|
| State | New |
| Headers | show |
| Series | Add QPIC SPI NAND driver | expand |
On 2/15/2024 7:18 PM, Md Sadre Alam wrote: > Add SPI NAND support for ipq9574 SoC. > > Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com> > --- > .../boot/dts/qcom/ipq9574-rdp-common.dtsi | 43 +++++++++++++++++++ > arch/arm64/boot/dts/qcom/ipq9574.dtsi | 27 ++++++++++++ > 2 files changed, 70 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi > index 91e104b0f865..5b54a027fa5d 100644 > --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi > +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi > @@ -139,6 +139,49 @@ gpio_leds_default: gpio-leds-default-state { > drive-strength = <8>; > bias-pull-up; > }; > + > + qpic_snand_default_state: qpic-snand-default-state { > + clock-pins { > + pins = "gpio5"; > + function = "qspi_clk"; > + drive-strength = <8>; > + bias-disable; > + }; > + > + cs-pins { > + pins = "gpio4"; > + function = "qspi_cs"; > + drive-strength = <8>; > + bias-disable; > + }; > + > + data-pins { > + pins = "gpio0", "gpio1", "gpio2"; As per the pinctrl driver[1], there are 4 data pins. [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/pinctrl/qcom/pinctrl-ipq9574.c#n296 > + function = "qspi_data"; > + drive-strength = <8>; > + bias-disable; > + }; > + }; > +}; > + > +&qpic_bam { > + status = "okay"; > +}; > + > +&qpic_nand { > + pinctrl-0 = <&qpic_snand_default_state>; > + pinctrl-names = "default"; > + status = "okay"; > + > + flash@0 { > + compatible = "spi-nand"; > + reg = <0>; > + #address-cells = <1>; > + #size-cells = <1>; > + nand-ecc-engine = <&qpic_nand>; > + nand-ecc-strength = <4>; > + nand-ecc-step-size = <512>; > + }; > }; > > &usb_0_dwc3 { > diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi > index 7f2e5cbf3bbb..d963dd2035dd 100644 > --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi > +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi > @@ -319,6 +319,33 @@ tcsr: syscon@1937000 { > reg = <0x01937000 0x21000>; > }; > > + qpic_bam: dma-controller@7984000 { Nodes should be ordered by unit address in ascending order. So please move these nodes to the right place. > + compatible = "qcom,bam-v1.7.0"; > + reg = <0x7984000 0x1c000>; address should be padded to 8 bytes. > + interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&gcc GCC_QPIC_AHB_CLK>; > + clock-names = "bam_clk"; > + #dma-cells = <1>; > + qcom,ee = <0>; > + status = "disabled"; > + }; > + > + qpic_nand: spi@79b0000 { > + compatible = "qcom,ipq9574-snand"; > + reg = <0x79b0000 0x10000>; Ditto.. > + #address-cells = <1>; > + #size-cells = <0>; > + clocks = <&gcc GCC_QPIC_CLK>, > + <&gcc GCC_QPIC_AHB_CLK>, > + <&gcc GCC_QPIC_IO_MACRO_CLK>; Fix the alignment. > + clock-names = "core", "aon", "iom"; > + dmas = <&qpic_bam 0>, > + <&qpic_bam 1>, > + <&qpic_bam 2>; Here as well. > + dma-names = "tx", "rx", "cmd"; > + status = "disabled"; > + }; > + > sdhc_1: mmc@7804000 { > compatible = "qcom,ipq9574-sdhci", "qcom,sdhci-msm-v5"; > reg = <0x07804000 0x1000>,
On 2/16/2024 9:10 PM, Kathiravan Thirumoorthy wrote: > > > On 2/15/2024 7:18 PM, Md Sadre Alam wrote: >> Add SPI NAND support for ipq9574 SoC. >> >> Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com> >> --- >> .../boot/dts/qcom/ipq9574-rdp-common.dtsi | 43 +++++++++++++++++++ >> arch/arm64/boot/dts/qcom/ipq9574.dtsi | 27 ++++++++++++ >> 2 files changed, 70 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi >> index 91e104b0f865..5b54a027fa5d 100644 >> --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi >> +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi >> @@ -139,6 +139,49 @@ gpio_leds_default: gpio-leds-default-state { >> drive-strength = <8>; >> bias-pull-up; >> }; >> + >> + qpic_snand_default_state: qpic-snand-default-state { >> + clock-pins { >> + pins = "gpio5"; >> + function = "qspi_clk"; >> + drive-strength = <8>; >> + bias-disable; >> + }; >> + >> + cs-pins { >> + pins = "gpio4"; >> + function = "qspi_cs"; >> + drive-strength = <8>; >> + bias-disable; >> + }; >> + >> + data-pins { >> + pins = "gpio0", "gpio1", "gpio2"; > > > As per the pinctrl driver[1], there are 4 data pins. > > [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/pinctrl/qcom/pinctrl-ipq9574.c#n296 Will fix in next patch. > > >> + function = "qspi_data"; >> + drive-strength = <8>; >> + bias-disable; >> + }; >> + }; >> +}; >> + >> +&qpic_bam { >> + status = "okay"; >> +}; >> + >> +&qpic_nand { >> + pinctrl-0 = <&qpic_snand_default_state>; >> + pinctrl-names = "default"; >> + status = "okay"; >> + >> + flash@0 { >> + compatible = "spi-nand"; >> + reg = <0>; >> + #address-cells = <1>; >> + #size-cells = <1>; >> + nand-ecc-engine = <&qpic_nand>; >> + nand-ecc-strength = <4>; >> + nand-ecc-step-size = <512>; >> + }; >> }; >> &usb_0_dwc3 { >> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi >> index 7f2e5cbf3bbb..d963dd2035dd 100644 >> --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi >> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi >> @@ -319,6 +319,33 @@ tcsr: syscon@1937000 { >> reg = <0x01937000 0x21000>; >> }; >> + qpic_bam: dma-controller@7984000 { > > > Nodes should be ordered by unit address in ascending order. So please move these nodes to the right place. Ok > > >> + compatible = "qcom,bam-v1.7.0"; >> + reg = <0x7984000 0x1c000>; > > > address should be padded to 8 bytes. Ok > >> + interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&gcc GCC_QPIC_AHB_CLK>; >> + clock-names = "bam_clk"; >> + #dma-cells = <1>; >> + qcom,ee = <0>; >> + status = "disabled"; >> + }; >> + >> + qpic_nand: spi@79b0000 { >> + compatible = "qcom,ipq9574-snand"; >> + reg = <0x79b0000 0x10000>; > > > Ditto.. Ok > >> + #address-cells = <1>; >> + #size-cells = <0>; >> + clocks = <&gcc GCC_QPIC_CLK>, >> + <&gcc GCC_QPIC_AHB_CLK>, >> + <&gcc GCC_QPIC_IO_MACRO_CLK>; > > > Fix the alignment. Ok > >> + clock-names = "core", "aon", "iom"; >> + dmas = <&qpic_bam 0>, >> + <&qpic_bam 1>, >> + <&qpic_bam 2>; > > > Here as well. Ok > > >> + dma-names = "tx", "rx", "cmd"; >> + status = "disabled"; >> + }; >> + >> sdhc_1: mmc@7804000 { >> compatible = "qcom,ipq9574-sdhci", "qcom,sdhci-msm-v5"; >> reg = <0x07804000 0x1000>,
diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi index 91e104b0f865..5b54a027fa5d 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi @@ -139,6 +139,49 @@ gpio_leds_default: gpio-leds-default-state { drive-strength = <8>; bias-pull-up; }; + + qpic_snand_default_state: qpic-snand-default-state { + clock-pins { + pins = "gpio5"; + function = "qspi_clk"; + drive-strength = <8>; + bias-disable; + }; + + cs-pins { + pins = "gpio4"; + function = "qspi_cs"; + drive-strength = <8>; + bias-disable; + }; + + data-pins { + pins = "gpio0", "gpio1", "gpio2"; + function = "qspi_data"; + drive-strength = <8>; + bias-disable; + }; + }; +}; + +&qpic_bam { + status = "okay"; +}; + +&qpic_nand { + pinctrl-0 = <&qpic_snand_default_state>; + pinctrl-names = "default"; + status = "okay"; + + flash@0 { + compatible = "spi-nand"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + nand-ecc-engine = <&qpic_nand>; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + }; }; &usb_0_dwc3 { diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index 7f2e5cbf3bbb..d963dd2035dd 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -319,6 +319,33 @@ tcsr: syscon@1937000 { reg = <0x01937000 0x21000>; }; + qpic_bam: dma-controller@7984000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x7984000 0x1c000>; + interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QPIC_AHB_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + status = "disabled"; + }; + + qpic_nand: spi@79b0000 { + compatible = "qcom,ipq9574-snand"; + reg = <0x79b0000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QPIC_CLK>, + <&gcc GCC_QPIC_AHB_CLK>, + <&gcc GCC_QPIC_IO_MACRO_CLK>; + clock-names = "core", "aon", "iom"; + dmas = <&qpic_bam 0>, + <&qpic_bam 1>, + <&qpic_bam 2>; + dma-names = "tx", "rx", "cmd"; + status = "disabled"; + }; + sdhc_1: mmc@7804000 { compatible = "qcom,ipq9574-sdhci", "qcom,sdhci-msm-v5"; reg = <0x07804000 0x1000>,
Add SPI NAND support for ipq9574 SoC. Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com> --- .../boot/dts/qcom/ipq9574-rdp-common.dtsi | 43 +++++++++++++++++++ arch/arm64/boot/dts/qcom/ipq9574.dtsi | 27 ++++++++++++ 2 files changed, 70 insertions(+)