| Message ID | 20231023171444.322311-2-dregan@broadcom.com |
|---|---|
| State | New |
| Headers | show |
| Series | [v4,1/4] mtd: rawnand: Add destructive operation | expand |
On 10/23/2023 10:14 AM, dregan@broadcom.com wrote: > From: David Regan <dregan@broadcom.com> > > Allow NAND controller to be responsible for write protect pin > handling during fast path and exec_op destructive operation > when controller_wp flag is set. > > Signed-off-by: David Regan <dregan@broadcom.com> > --- > Changes in v4: none > > Changes in v3: update comments > > Changes in v2: none > --- > drivers/mtd/nand/raw/nand_base.c | 4 ++++ > include/linux/mtd/rawnand.h | 2 ++ > 2 files changed, 6 insertions(+) > Reviewed-by: William Zhang <william.zhang@broadcom.com>
diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index 47cc2c35153b..38ed0ced5b8e 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -367,6 +367,10 @@ static int nand_check_wp(struct nand_chip *chip) if (chip->options & NAND_BROKEN_XD) return 0; + /* controller responsible for NAND write protect */ + if (chip->controller->controller_wp) + return 0; + /* Check the WP bit */ ret = nand_status_op(chip, &status); if (ret) diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h index 31aceda8616c..fcad94aa0515 100644 --- a/include/linux/mtd/rawnand.h +++ b/include/linux/mtd/rawnand.h @@ -1111,6 +1111,7 @@ struct nand_controller_ops { * the bus without restarting an entire read operation nor * changing the column. * @supported_op.cont_read: The controller supports sequential cache reads. + * @controller_wp: the controller is in charge of handling the WP pin. */ struct nand_controller { struct mutex lock; @@ -1119,6 +1120,7 @@ struct nand_controller { unsigned int data_only_read: 1; unsigned int cont_read: 1; } supported_op; + bool controller_wp; }; static inline void nand_controller_init(struct nand_controller *nfc)