[v1] mtd: spinand: add support for FORESEE F35SQA002G

Add support for FORESEE F35SQA002G SPI NAND.
Datasheet:
  https://www.longsys.com/uploads/LM-00006FORESEEF35SQA002GDatasheet_1650183701.pdf

Signed-off-by: Martin Kurbanov <mmkurbanov@salutedevices.com>
---
 drivers/mtd/nand/spi/Makefile  |   2 +-
 drivers/mtd/nand/spi/core.c    |   1 +
 drivers/mtd/nand/spi/foresee.c | 101 +++++++++++++++++++++++++++++++++
 include/linux/mtd/spinand.h    |   1 +
 4 files changed, 104 insertions(+), 1 deletion(-)
 create mode 100644 drivers/mtd/nand/spi/foresee.c

Hi Martin,

mmkurbanov@salutedevices.com wrote on Fri, 29 Sep 2023 17:49:34 +0300:

> Add support for FORESEE F35SQA002G SPI NAND.
> Datasheet:
>   https://www.longsys.com/uploads/LM-00006FORESEEF35SQA002GDatasheet_1650183701.pdf
> 
> Signed-off-by: Martin Kurbanov <mmkurbanov@salutedevices.com>
> ---
>  drivers/mtd/nand/spi/Makefile  |   2 +-
>  drivers/mtd/nand/spi/core.c    |   1 +
>  drivers/mtd/nand/spi/foresee.c | 101 +++++++++++++++++++++++++++++++++
>  include/linux/mtd/spinand.h    |   1 +
>  4 files changed, 104 insertions(+), 1 deletion(-)
>  create mode 100644 drivers/mtd/nand/spi/foresee.c
> 
> diff --git a/drivers/mtd/nand/spi/Makefile b/drivers/mtd/nand/spi/Makefile
> index cd8b66bf7740..19cc77288ebb 100644
> --- a/drivers/mtd/nand/spi/Makefile
> +++ b/drivers/mtd/nand/spi/Makefile
> @@ -1,4 +1,4 @@
>  # SPDX-License-Identifier: GPL-2.0
> -spinand-objs := core.o alliancememory.o ato.o esmt.o gigadevice.o macronix.o
> +spinand-objs := core.o alliancememory.o ato.o esmt.o foresee.o gigadevice.o macronix.o
>  spinand-objs += micron.o paragon.o toshiba.o winbond.o xtx.o
>  obj-$(CONFIG_MTD_SPI_NAND) += spinand.o
> diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c
> index 393ff37f0d23..849ccfedbc72 100644
> --- a/drivers/mtd/nand/spi/core.c
> +++ b/drivers/mtd/nand/spi/core.c
> @@ -940,6 +940,7 @@ static const struct spinand_manufacturer *spinand_manufacturers[] = {
>  	&alliancememory_spinand_manufacturer,
>  	&ato_spinand_manufacturer,
>  	&esmt_c8_spinand_manufacturer,
> +	&foresee_spinand_manufacturer,
>  	&gigadevice_spinand_manufacturer,
>  	&macronix_spinand_manufacturer,
>  	&micron_spinand_manufacturer,
> diff --git a/drivers/mtd/nand/spi/foresee.c b/drivers/mtd/nand/spi/foresee.c
> new file mode 100644
> index 000000000000..55d4ff1f091a
> --- /dev/null
> +++ b/drivers/mtd/nand/spi/foresee.c
> @@ -0,0 +1,101 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (c) 2023, SberDevices. All Rights Reserved.
> + *
> + * Author: Martin Kurbanov <mmkurbanov@salutedevices.com>
> + */
> +
> +#include <linux/device.h>
> +#include <linux/kernel.h>
> +#include <linux/mtd/spinand.h>
> +
> +#define SPINAND_MFR_FORESEE		0xCD
> +
> +static SPINAND_OP_VARIANTS(read_cache_variants,
> +		SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
> +		SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
> +		SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
> +		SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
> +
> +static SPINAND_OP_VARIANTS(write_cache_variants,
> +		SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
> +		SPINAND_PROG_LOAD(true, 0, NULL, 0));
> +
> +static SPINAND_OP_VARIANTS(update_cache_variants,
> +		SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
> +		SPINAND_PROG_LOAD(false, 0, NULL, 0));
> +
> +static int f35sqa002g_ooblayout_ecc(struct mtd_info *mtd, int section,
> +				    struct mtd_oob_region *region)
> +{
> +	return -ERANGE;
> +}
> +
> +static int f35sqa002g_ooblayout_free(struct mtd_info *mtd, int section,
> +				     struct mtd_oob_region *region)
> +{
> +	/* XXX: It is not possible to partially write to this OOB area, as both
> +	 * the main and OOB areas are protected by ECC. The user needs to
> +	 * program both the main area and OOB area at one programming time,
> +	 * so that the ECC parity code can be calculated properly.
> +	 */

Is this comment really needed? I believe it could be dropped, unless
you are really experiencing strange subpage write attempts?

> +
> +	if (section)
> +		return -ERANGE;
> +
> +	/* Reserve 2 bytes for the BBM. */
> +	region->offset = 2;
> +	region->length = 62;
> +
> +	return 0;
> +}
> +
> +static const struct mtd_ooblayout_ops f35sqa002g_ooblayout = {
> +	.ecc = f35sqa002g_ooblayout_ecc,
> +	.free = f35sqa002g_ooblayout_free,
> +};
> +
> +static int f35sqa002g_ecc_get_status(struct spinand_device *spinand, u8 status)
> +{
> +	struct nand_device *nand = spinand_to_nand(spinand);
> +
> +	switch (status & STATUS_ECC_MASK) {
> +	case STATUS_ECC_NO_BITFLIPS:
> +		return 0;
> +
> +	case STATUS_ECC_HAS_BITFLIPS:
> +		return nanddev_get_ecc_conf(nand)->strength;
> +
> +	default:
> +		break;
> +	}
> +
> +	/* More than 1-bit error was detected in one or more sectors and
> +	 * cannot be corrected.
> +	 */
> +	return -EBADMSG;
> +}
> +
> +static const struct spinand_info foresee_spinand_table[] = {
> +	SPINAND_INFO("F35SQA002G",
> +		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x72, 0x72),
> +		     NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 1, 1, 1),
> +		     NAND_ECCREQ(1, 512),
> +		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
> +					      &write_cache_variants,
> +					      &update_cache_variants),
> +		     SPINAND_HAS_QE_BIT,
> +		     SPINAND_ECCINFO(&f35sqa002g_ooblayout,
> +				     f35sqa002g_ecc_get_status)),
> +};
> +
> +static const struct spinand_manufacturer_ops foresee_spinand_manuf_ops = {
> +};
> +
> +const struct spinand_manufacturer foresee_spinand_manufacturer = {
> +	.id = SPINAND_MFR_FORESEE,
> +	.name = "FORESEE",
> +	.chips = foresee_spinand_table,
> +	.nchips = ARRAY_SIZE(foresee_spinand_table),
> +	.ops = &foresee_spinand_manuf_ops,
> +};
> diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h
> index 3e285c09d16d..badb4c1ac079 100644
> --- a/include/linux/mtd/spinand.h
> +++ b/include/linux/mtd/spinand.h
> @@ -263,6 +263,7 @@ struct spinand_manufacturer {
>  extern const struct spinand_manufacturer alliancememory_spinand_manufacturer;
>  extern const struct spinand_manufacturer ato_spinand_manufacturer;
>  extern const struct spinand_manufacturer esmt_c8_spinand_manufacturer;
> +extern const struct spinand_manufacturer foresee_spinand_manufacturer;
>  extern const struct spinand_manufacturer gigadevice_spinand_manufacturer;
>  extern const struct spinand_manufacturer macronix_spinand_manufacturer;
>  extern const struct spinand_manufacturer micron_spinand_manufacturer;

Otherwise looks good.

Thanks,
Miquèl

Hi Miquel,
Thanks for your review.

On 02.10.2023 12:44, Miquel Raynal wrote:
> Hi Martin,
>> +static int f35sqa002g_ooblayout_free(struct mtd_info *mtd, int section,
>> +				     struct mtd_oob_region *region)
>> +{
>> +	/* XXX: It is not possible to partially write to this OOB area, as both
>> +	 * the main and OOB areas are protected by ECC. The user needs to
>> +	 * program both the main area and OOB area at one programming time,
>> +	 * so that the ECC parity code can be calculated properly.
>> +	 */
> 
> Is this comment really needed? I believe it could be dropped, unless
> you are really experiencing strange subpage write attempts?

If you write separately to the main area and the OOB area. This is the
case with many SPI NAND chips, I agree that this comment can be dropped.

Hi Martin,

mmkurbanov@salutedevices.com wrote on Mon, 2 Oct 2023 13:18:18 +0300:

> Hi Miquel,
> Thanks for your review.
> 
> On 02.10.2023 12:44, Miquel Raynal wrote:
> > Hi Martin,  
> >> +static int f35sqa002g_ooblayout_free(struct mtd_info *mtd, int section,
> >> +				     struct mtd_oob_region *region)
> >> +{
> >> +	/* XXX: It is not possible to partially write to this OOB area, as both
> >> +	 * the main and OOB areas are protected by ECC. The user needs to
> >> +	 * program both the main area and OOB area at one programming time,
> >> +	 * so that the ECC parity code can be calculated properly.
> >> +	 */  
> > 
> > Is this comment really needed? I believe it could be dropped, unless
> > you are really experiencing strange subpage write attempts?  
> 
> If you write separately to the main area and the OOB area. This is the
> case with many SPI NAND chips, I agree that this comment can be dropped.
> 

All NAND chips have this limitation actually. I guess you can just get
rid of the comment. The rest looks ok.

Thanks, Miquèl