| Message ID | 20211217134442.497950-2-tudor.ambarus@microchip.com |
|---|---|
| State | Superseded |
| Delegated to: | Ambarus Tudor |
| Headers | show |
| Series | [v3,1/2] mtd: spi-nor: core: Introduce SPI_NOR_SOFT_RESET flash_info fixup_flag | expand |
On 12/17/21 3:44 PM, Tudor Ambarus wrote: > mx66lm1g45g supports just 1-1-1, 8-8-8 and 8d-8d-8d modes. There are > versions of mx66lm1g45g which do not support SFDP, thus use > SPI_NOR_SKIP_SFDP. The RDID command issued through the octal peripheral > interface outputs data always in STR mode for whatever reason. Since > 8d-8d-8s is not common, avoid reading the ID when enabling the octal dtr > mode. Instead, read back the CR2 to check if the switch was successful. > Tested in 1-1-1 and 8d-8d-8d modes using sama7g5 QSPI IP. > > Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> > --- > v3: > - resend the patch, this time prefixed with v3 > - drop setting of dummy cycles, use the default value > - avoid odd lengths in octal dtr mode > - s/8d-8d-8d/8D-8D-8D > > v2: SPI_NOR_SOFT_RESET as a FIXUP_FLAG > > # cat /sys/devices/platform/soc/e080c000.spi/spi_master/spi1/spi1.0/spi-nor/jedec_id > c2853b > # cat /sys/devices/platform/soc/e080c000.spi/spi_master/spi1/spi1.0/spi-nor/manufacturer > macronix > # cat /sys/devices/platform/soc/e080c000.spi/spi_master/spi1/spi1.0/spi-nor/partname > mx66lm1g45g > # cat /sys/devices/platform/soc/e080c000.spi/spi_master/spi1/spi1.0/spi-nor/sfdp > cat: can't open '/sys/devices/platform/soc/e080c000.spi/spi_master/spi1/spi1.0/spi-nor/sfdp': No such file or directory > > drivers/mtd/spi-nor/macronix.c | 96 ++++++++++++++++++++++++++++++++++ > 1 file changed, 96 insertions(+) > > diff --git a/drivers/mtd/spi-nor/macronix.c b/drivers/mtd/spi-nor/macronix.c > index 67aaa83038b6..4c672deb1d1c 100644 > --- a/drivers/mtd/spi-nor/macronix.c > +++ b/drivers/mtd/spi-nor/macronix.c > @@ -32,6 +32,95 @@ static struct spi_nor_fixups mx25l25635_fixups = { > .post_bfpt = mx25l25635_post_bfpt_fixups, > }; > > +#define SPINOR_OP_READ_CR2 0x71 > +#define SPINOR_OP_WRITE_CR2 0x72 > +#define SPINOR_OP_MX_DTR_RD 0xee > + > +#define SPINOR_REG_CR2_MODE_ADDR 0 > +#define SPINOR_REG_CR2_DTR_OPI_ENABLE BIT(1) > +#define SPINOR_REG_CR2_SPI 0 > + > +static int spi_nor_macronix_octal_dtr_enable(struct spi_nor *nor, bool enable) > +{ > + u8 *buf = nor->bouncebuf; > + struct spi_mem_op op; > + int ret; > + > + /* Set/unset the octal and DTR enable bits. */ > + if (enable) { > + buf[0] = SPINOR_REG_CR2_DTR_OPI_ENABLE; > + } else { > + /* > + * The register is one byte wide, but the one byte transactions > + * are not allowed in 8D-8D-8D mode. Since there is no register > + * at the next location, just initialize the value to zero and > + * let the transaction go on. > + */ actually CR2 is indexed by address, from 00000000h to 80000000h. And macronix states that "All addresses not shown in the table must keep value unchanged.". So I should maybe read what's at address one, and when disabling octal to use the value read, so that I don't change undefined values. Meh. > + buf[0] = SPINOR_REG_CR2_SPI; > + buf[1] = 0; > + } > + > + op = (struct spi_mem_op) > + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRITE_CR2, 1), > + SPI_MEM_OP_ADDR(4, SPINOR_REG_CR2_MODE_ADDR, 1), > + SPI_MEM_OP_NO_DUMMY, > + SPI_MEM_OP_DATA_OUT(enable ? 1 : 2, buf, 1)); > + if (!enable) > + spi_nor_spimem_setup_op(nor, &op, SNOR_PROTO_8_8_8_DTR); > + > + ret = spi_nor_write_enable(nor); > + if (ret) > + return ret; > + > + ret = spi_mem_exec_op(nor->spimem, &op); > + if (ret) > + return ret; > + > + /* Read back CR2 to make sure the switch was successful. */ > + op = (struct spi_mem_op) > + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ_CR2, 1), > + SPI_MEM_OP_ADDR(4, SPINOR_REG_CR2_MODE_ADDR, 1), > + SPI_MEM_OP_DUMMY(enable ? 4 : 0, 1), > + SPI_MEM_OP_DATA_IN(enable ? 2 : 1, buf, 1)); > + if (enable) > + spi_nor_spimem_setup_op(nor, &op, SNOR_PROTO_8_8_8_DTR); > + > + ret = spi_mem_exec_op(nor->spimem, &op); > + if (ret) > + return ret; > + > + if (enable) { > + if (buf[0] != SPINOR_REG_CR2_DTR_OPI_ENABLE) { > + dev_dbg(nor->dev, "Failed to enable 8D-8D-8D mode.\n"); > + return -EINVAL; > + } > + } else if (buf[0] != SPINOR_REG_CR2_SPI) { > + dev_dbg(nor->dev, "Failed to disable 8D-8D-8D mode.\n"); > + return -EINVAL; > + } > + > + return 0; > +} > + > +static void mx66lm1g45g_late_init(struct spi_nor *nor) > +{ > + nor->params->octal_dtr_enable = spi_nor_macronix_octal_dtr_enable; > + > + /* Set the Fast Read settings. */ > + nor->params->hwcaps.mask |= SNOR_HWCAPS_READ_8_8_8_DTR; > + spi_nor_set_read_settings(&nor->params->reads[SNOR_CMD_READ_8_8_8_DTR], > + 0, 20, SPINOR_OP_MX_DTR_RD, > + SNOR_PROTO_8_8_8_DTR); > + > + nor->cmd_ext_type = SPI_NOR_EXT_INVERT; > + nor->params->rdsr_dummy = 4; > + nor->params->rdsr_addr_nbytes = 4; > +} > + > +static struct spi_nor_fixups mx66lm1g45g_fixups = { > + .late_init = mx66lm1g45g_late_init, > +}; > + > static const struct flash_info macronix_parts[] = { > /* Macronix */ > { "mx25l512e", INFO(0xc22010, 0, 64 * 1024, 1) > @@ -100,6 +189,13 @@ static const struct flash_info macronix_parts[] = { > { "mx66u2g45g", INFO(0xc2253c, 0, 64 * 1024, 4096) > NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) > FIXUP_FLAGS(SPI_NOR_4B_OPCODES) }, > + { "mx66lm1g45g", INFO(0xc2853b, 0, 64 * 1024, 2048) > + NO_SFDP_FLAGS(SPI_NOR_SKIP_SFDP | SECT_4K | > + SPI_NOR_OCTAL_DTR_READ | SPI_NOR_OCTAL_DTR_PP) > + FIXUP_FLAGS(SPI_NOR_4B_OPCODES | SPI_NOR_IO_MODE_EN_VOLATILE | > + SPI_NOR_SOFT_RESET) > + .fixups = &mx66lm1g45g_fixups, > + }, > }; > > static void macronix_default_init(struct spi_nor *nor) >
diff --git a/drivers/mtd/spi-nor/macronix.c b/drivers/mtd/spi-nor/macronix.c index 67aaa83038b6..4c672deb1d1c 100644 --- a/drivers/mtd/spi-nor/macronix.c +++ b/drivers/mtd/spi-nor/macronix.c @@ -32,6 +32,95 @@ static struct spi_nor_fixups mx25l25635_fixups = { .post_bfpt = mx25l25635_post_bfpt_fixups, }; +#define SPINOR_OP_READ_CR2 0x71 +#define SPINOR_OP_WRITE_CR2 0x72 +#define SPINOR_OP_MX_DTR_RD 0xee + +#define SPINOR_REG_CR2_MODE_ADDR 0 +#define SPINOR_REG_CR2_DTR_OPI_ENABLE BIT(1) +#define SPINOR_REG_CR2_SPI 0 + +static int spi_nor_macronix_octal_dtr_enable(struct spi_nor *nor, bool enable) +{ + u8 *buf = nor->bouncebuf; + struct spi_mem_op op; + int ret; + + /* Set/unset the octal and DTR enable bits. */ + if (enable) { + buf[0] = SPINOR_REG_CR2_DTR_OPI_ENABLE; + } else { + /* + * The register is one byte wide, but the one byte transactions + * are not allowed in 8D-8D-8D mode. Since there is no register + * at the next location, just initialize the value to zero and + * let the transaction go on. + */ + buf[0] = SPINOR_REG_CR2_SPI; + buf[1] = 0; + } + + op = (struct spi_mem_op) + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRITE_CR2, 1), + SPI_MEM_OP_ADDR(4, SPINOR_REG_CR2_MODE_ADDR, 1), + SPI_MEM_OP_NO_DUMMY, + SPI_MEM_OP_DATA_OUT(enable ? 1 : 2, buf, 1)); + if (!enable) + spi_nor_spimem_setup_op(nor, &op, SNOR_PROTO_8_8_8_DTR); + + ret = spi_nor_write_enable(nor); + if (ret) + return ret; + + ret = spi_mem_exec_op(nor->spimem, &op); + if (ret) + return ret; + + /* Read back CR2 to make sure the switch was successful. */ + op = (struct spi_mem_op) + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ_CR2, 1), + SPI_MEM_OP_ADDR(4, SPINOR_REG_CR2_MODE_ADDR, 1), + SPI_MEM_OP_DUMMY(enable ? 4 : 0, 1), + SPI_MEM_OP_DATA_IN(enable ? 2 : 1, buf, 1)); + if (enable) + spi_nor_spimem_setup_op(nor, &op, SNOR_PROTO_8_8_8_DTR); + + ret = spi_mem_exec_op(nor->spimem, &op); + if (ret) + return ret; + + if (enable) { + if (buf[0] != SPINOR_REG_CR2_DTR_OPI_ENABLE) { + dev_dbg(nor->dev, "Failed to enable 8D-8D-8D mode.\n"); + return -EINVAL; + } + } else if (buf[0] != SPINOR_REG_CR2_SPI) { + dev_dbg(nor->dev, "Failed to disable 8D-8D-8D mode.\n"); + return -EINVAL; + } + + return 0; +} + +static void mx66lm1g45g_late_init(struct spi_nor *nor) +{ + nor->params->octal_dtr_enable = spi_nor_macronix_octal_dtr_enable; + + /* Set the Fast Read settings. */ + nor->params->hwcaps.mask |= SNOR_HWCAPS_READ_8_8_8_DTR; + spi_nor_set_read_settings(&nor->params->reads[SNOR_CMD_READ_8_8_8_DTR], + 0, 20, SPINOR_OP_MX_DTR_RD, + SNOR_PROTO_8_8_8_DTR); + + nor->cmd_ext_type = SPI_NOR_EXT_INVERT; + nor->params->rdsr_dummy = 4; + nor->params->rdsr_addr_nbytes = 4; +} + +static struct spi_nor_fixups mx66lm1g45g_fixups = { + .late_init = mx66lm1g45g_late_init, +}; + static const struct flash_info macronix_parts[] = { /* Macronix */ { "mx25l512e", INFO(0xc22010, 0, 64 * 1024, 1) @@ -100,6 +189,13 @@ static const struct flash_info macronix_parts[] = { { "mx66u2g45g", INFO(0xc2253c, 0, 64 * 1024, 4096) NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) FIXUP_FLAGS(SPI_NOR_4B_OPCODES) }, + { "mx66lm1g45g", INFO(0xc2853b, 0, 64 * 1024, 2048) + NO_SFDP_FLAGS(SPI_NOR_SKIP_SFDP | SECT_4K | + SPI_NOR_OCTAL_DTR_READ | SPI_NOR_OCTAL_DTR_PP) + FIXUP_FLAGS(SPI_NOR_4B_OPCODES | SPI_NOR_IO_MODE_EN_VOLATILE | + SPI_NOR_SOFT_RESET) + .fixups = &mx66lm1g45g_fixups, + }, }; static void macronix_default_init(struct spi_nor *nor)
mx66lm1g45g supports just 1-1-1, 8-8-8 and 8d-8d-8d modes. There are versions of mx66lm1g45g which do not support SFDP, thus use SPI_NOR_SKIP_SFDP. The RDID command issued through the octal peripheral interface outputs data always in STR mode for whatever reason. Since 8d-8d-8s is not common, avoid reading the ID when enabling the octal dtr mode. Instead, read back the CR2 to check if the switch was successful. Tested in 1-1-1 and 8d-8d-8d modes using sama7g5 QSPI IP. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> --- v3: - resend the patch, this time prefixed with v3 - drop setting of dummy cycles, use the default value - avoid odd lengths in octal dtr mode - s/8d-8d-8d/8D-8D-8D v2: SPI_NOR_SOFT_RESET as a FIXUP_FLAG # cat /sys/devices/platform/soc/e080c000.spi/spi_master/spi1/spi1.0/spi-nor/jedec_id c2853b # cat /sys/devices/platform/soc/e080c000.spi/spi_master/spi1/spi1.0/spi-nor/manufacturer macronix # cat /sys/devices/platform/soc/e080c000.spi/spi_master/spi1/spi1.0/spi-nor/partname mx66lm1g45g # cat /sys/devices/platform/soc/e080c000.spi/spi_master/spi1/spi1.0/spi-nor/sfdp cat: can't open '/sys/devices/platform/soc/e080c000.spi/spi_master/spi1/spi1.0/spi-nor/sfdp': No such file or directory drivers/mtd/spi-nor/macronix.c | 96 ++++++++++++++++++++++++++++++++++ 1 file changed, 96 insertions(+)