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[2/3] mtd: spi-nor: sst: add missing write_enable

Message ID 20200911144703.25409-3-m.felsch@pengutronix.de
State Changes Requested
Delegated to: Vignesh R
Headers show
Series MTD: SST SPI-NOR fixes | expand

Commit Message

Marco Felsch Sept. 11, 2020, 2:47 p.m. UTC 
According the datasheet [1] the WEL is automatically reset after the
Byte-Program instruction completion. So if we program the device with
byte-size set to 32 and starting from an odd address only the first and
the last byte is written. Fix this by (re-)anble the write support for
the first SPINOR_OP_AAI_WP sequence.

[1] http://ww1.microchip.com/downloads/en/DeviceDoc/20005044C.pdf;
    "4.3.2 WRITE ENABLE LATCH (WEL)"

Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
---
 drivers/mtd/spi-nor/sst.c | 7 +++++++
 1 file changed, 7 insertions(+)
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Patch

diff --git a/drivers/mtd/spi-nor/sst.c b/drivers/mtd/spi-nor/sst.c
index e0af6d25d573..644252e27a2a 100644
--- a/drivers/mtd/spi-nor/sst.c
+++ b/drivers/mtd/spi-nor/sst.c
@@ -79,6 +79,13 @@  static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
 
 	/* Write out most of the data here. */
 	for (; actual < len - 1; actual += 2) {
+		/* Enable write support if odd address was written before */
+		if (actual == 1) {
+			ret = spi_nor_write_enable(nor);
+			if (ret)
+				goto out;
+		}
+
 		nor->program_opcode = SPINOR_OP_AAI_WP;
 
 		/* write two bytes. */