@@ -38,6 +38,9 @@ properties:
"#clock-cells":
const: 0
+ clock-output-names:
+ maxItems: 1
+
# The BD71847 abd BD71850 support two different HW states as reset target
# states. States are called as SNVS and READY. At READY state all the PMIC
# power outputs go down and OTP is reload. At the SNVS state all other logic
@@ -116,12 +119,14 @@ required:
- compatible
- reg
- interrupts
- - clocks
- - "#clock-cells"
- regulators
additionalProperties: false
+dependencies:
+ '#clock-cells': [clocks]
+ clocks: ['#clock-cells']
+
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>