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Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kBhfK-0000NW-VS; Fri, 28 Aug 2020 16:55:51 +0000 Received: from mail.kernel.org ([198.145.29.99]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kBha3-0005bh-UC; Fri, 28 Aug 2020 16:50:25 +0000 Received: from kozik-lap.mshome.net (unknown [194.230.155.216]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id A1DC820C56; Fri, 28 Aug 2020 16:50:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1598633422; bh=Cgxn33agiAyp87HeECnZVMhxGfb2+DrRvu3F+O4k4xU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=XMecWnAgOXRnqFZguFNZP++EQZeOKRRS5Pe+Zk8bSrrUsCjXle74AErcIw7+ZWsoF ervXUHTa8lWgRKeZ7FLmxkSRfE3N+9xeZjqe8jJFQWe4m2Vyjhj0irN8yl5C6TFrFF 3KKcfKi81CTMl2bK/i/TBBzarDVDs/FzlFRWjCSY= From: Krzysztof Kozlowski To: Lee Jones , Rob Herring , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Anson Huang , Matti Vaittinen , Han Xu , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 15/19] arm64: dts: imx8mq-phanbell: Align pin configuration group names with schema Date: Fri, 28 Aug 2020 18:47:46 +0200 Message-Id: <20200828164750.10377-16-krzk@kernel.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200828164750.10377-1-krzk@kernel.org> References: <20200828164750.10377-1-krzk@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200828_125024_191895_110A3A7D X-CRM114-Status: GOOD ( 12.88 ) X-Spam-Score: -6.2 (------) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-6.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at https://www.dnswl.org/, high trust [198.145.29.99 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -1.0 DKIMWL_WL_HIGH DKIMwl.org - Whitelisted High sender X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Krzysztof Kozlowski MIME-Version: 1.0 Sender: "linux-mtd" Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org Device tree schema expects pin configuration groups to end with 'grp' suffix, otherwise dtbs_check complain with a warning like: ... do not match any of the regexes: 'grp$', 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts index 3f541ddf0768..d6d3a3d5abc3 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts @@ -365,7 +365,7 @@ >; }; - pinctrl_pmic: pmicirq { + pinctrl_pmic: pmicirqgrp { fsl,pins = < MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 >; @@ -395,7 +395,7 @@ >; }; - pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { fsl,pins = < MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5 @@ -412,7 +412,7 @@ >; }; - pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { fsl,pins = < MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7 @@ -429,7 +429,7 @@ >; }; - pinctrl_usdhc2_gpio: usdhc2grpgpio { + pinctrl_usdhc2_gpio: usdhc2gpiogrp { fsl,pins = < MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 @@ -448,7 +448,7 @@ >; }; - pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { fsl,pins = < MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5 @@ -460,7 +460,7 @@ >; }; - pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { fsl,pins = < MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7