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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Fri, 4 Oct 2019 13:09:39 +0100 Received: from d06av25.portsmouth.uk.ibm.com (d06av25.portsmouth.uk.ibm.com [9.149.105.61]) by b06cxnps4074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x94C9cbv50528396 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 4 Oct 2019 12:09:38 GMT Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 11B7911C04C; Fri, 4 Oct 2019 12:09:38 +0000 (GMT) Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id E7C0611C04A; Fri, 4 Oct 2019 12:09:37 +0000 (GMT) Received: from smtp.tls.ibm.com (unknown [9.101.4.1]) by d06av25.portsmouth.uk.ibm.com (Postfix) with ESMTP; Fri, 4 Oct 2019 12:09:37 +0000 (GMT) Received: from yukon.kaod.org.com (sig-9-145-169-184.de.ibm.com [9.145.169.184]) by smtp.tls.ibm.com (Postfix) with ESMTP id D21952201B7; Fri, 4 Oct 2019 14:09:36 +0200 (CEST) From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: linux-mtd@lists.infradead.org, Tudor Ambarus Subject: [PATCH 14/16] mtd: spi-nor: aspeed: Introduce training operations per platform Date: Fri, 4 Oct 2019 14:09:32 +0200 X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191004115919.20788-1-clg@kaod.org> References: <20191004115919.20788-1-clg@kaod.org> MIME-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 19100412-0020-0000-0000-00000374FF71 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19100412-0021-0000-0000-000021CB0E95 Message-Id: <20191004120934.21662-1-clg@kaod.org> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-10-04_06:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=2 phishscore=0 bulkscore=0 spamscore=0 clxscore=1034 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=646 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1908290000 definitions=main-1910040113 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191004_050948_430470_40C9A4DA X-CRM114-Status: GOOD ( 23.26 ) X-Spam-Score: 0.3 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (0.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at https://www.dnswl.org/, low trust [148.163.158.5 listed in list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 1.0 SPF_SOFTFAIL SPF: sender does not match SPF record (softfail) X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Vignesh Raghavendra , linux-aspeed@lists.ozlabs.org, Andrew Jeffery , Richard Weinberger , Marek Vasut , Joel Stanley , Miquel Raynal , Brian Norris , David Woodhouse , linux-arm-kernel@lists.infradead.org, =?utf-8?q?C=C3=A9dric_Le_Goater?= Sender: "linux-mtd" Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org The read timing compensation register records the read delay settings for a range of HCLK. Its encoding is different on the AST2600 and the read training will be slightly more complex. Signed-off-by: Cédric Le Goater Reviewed-by: Andrew Jeffery --- drivers/mtd/spi-nor/aspeed-smc.c | 23 ++++++++++++++++++++--- 1 file changed, 20 insertions(+), 3 deletions(-) diff --git a/drivers/mtd/spi-nor/aspeed-smc.c b/drivers/mtd/spi-nor/aspeed-smc.c index fad08738e534..85b7ff3bcc91 100644 --- a/drivers/mtd/spi-nor/aspeed-smc.c +++ b/drivers/mtd/spi-nor/aspeed-smc.c @@ -41,9 +41,13 @@ struct aspeed_smc_info { u8 we0; /* shift for write enable bit for CE0 */ u8 ctl0; /* offset in regs of ctl for CE0 */ u8 timing; /* offset in regs of timing */ + u32 hdiv_max; /* Max HCLK divisor on read timing reg */ void (*set_4b)(struct aspeed_smc_chip *chip); int (*optimize_read)(struct aspeed_smc_chip *chip, u32 max_freq); + int (*calibrate)(struct aspeed_smc_chip *chip, u32 hdiv, + const u8 *golden_buf, u8 *test_buf); + u32 (*segment_start)(struct aspeed_smc_controller *controller, u32 reg); u32 (*segment_end)(struct aspeed_smc_controller *controller, u32 reg); u32 (*segment_reg)(struct aspeed_smc_controller *controller, @@ -54,6 +58,8 @@ static void aspeed_smc_chip_set_4b_spi_2400(struct aspeed_smc_chip *chip); static void aspeed_smc_chip_set_4b(struct aspeed_smc_chip *chip); static int aspeed_smc_optimize_read(struct aspeed_smc_chip *chip, u32 max_freq); +static int aspeed_smc_calibrate_reads(struct aspeed_smc_chip *chip, u32 hdiv, + const u8 *golden_buf, u8 *test_buf); static u32 aspeed_smc_segment_start(struct aspeed_smc_controller *controller, u32 reg); @@ -69,8 +75,10 @@ static const struct aspeed_smc_info fmc_2400_info = { .we0 = 16, .ctl0 = 0x10, .timing = 0x94, + .hdiv_max = 1, .set_4b = aspeed_smc_chip_set_4b, .optimize_read = aspeed_smc_optimize_read, + .calibrate = aspeed_smc_calibrate_reads, .segment_start = aspeed_smc_segment_start, .segment_end = aspeed_smc_segment_end, .segment_reg = aspeed_smc_segment_reg, @@ -83,8 +91,10 @@ static const struct aspeed_smc_info spi_2400_info = { .we0 = 0, .ctl0 = 0x04, .timing = 0x14, + .hdiv_max = 1, .set_4b = aspeed_smc_chip_set_4b_spi_2400, .optimize_read = aspeed_smc_optimize_read, + .calibrate = aspeed_smc_calibrate_reads, /* No segment registers */ }; @@ -95,8 +105,10 @@ static const struct aspeed_smc_info fmc_2500_info = { .we0 = 16, .ctl0 = 0x10, .timing = 0x94, + .hdiv_max = 1, .set_4b = aspeed_smc_chip_set_4b, .optimize_read = aspeed_smc_optimize_read, + .calibrate = aspeed_smc_calibrate_reads, .segment_start = aspeed_smc_segment_start, .segment_end = aspeed_smc_segment_end, .segment_reg = aspeed_smc_segment_reg, @@ -109,8 +121,10 @@ static const struct aspeed_smc_info spi_2500_info = { .we0 = 16, .ctl0 = 0x10, .timing = 0x94, + .hdiv_max = 1, .set_4b = aspeed_smc_chip_set_4b, .optimize_read = aspeed_smc_optimize_read, + .calibrate = aspeed_smc_calibrate_reads, .segment_start = aspeed_smc_segment_start, .segment_end = aspeed_smc_segment_end, .segment_reg = aspeed_smc_segment_reg, @@ -1022,6 +1036,8 @@ static u32 aspeed_smc_default_read(struct aspeed_smc_chip *chip) static int aspeed_smc_optimize_read(struct aspeed_smc_chip *chip, u32 max_freq) { + struct aspeed_smc_controller *controller = chip->controller; + const struct aspeed_smc_info *info = controller->info; u8 *golden_buf, *test_buf; int i, rc, best_div = -1; u32 save_read_val = chip->ctl_val[smc_read]; @@ -1054,7 +1070,8 @@ static int aspeed_smc_optimize_read(struct aspeed_smc_chip *chip, } /* Now we iterate the HCLK dividers until we find our breaking point */ - for (i = ARRAY_SIZE(aspeed_smc_hclk_divs); i > 0; i--) { + for (i = ARRAY_SIZE(aspeed_smc_hclk_divs); + i > info->hdiv_max - 1; i--) { u32 tv, freq; /* Compare timing to max */ @@ -1065,8 +1082,8 @@ static int aspeed_smc_optimize_read(struct aspeed_smc_chip *chip, /* Set the timing */ tv = chip->ctl_val[smc_read] | ASPEED_SMC_HCLK_DIV(i); writel(tv, chip->ctl); - dev_dbg(chip->nor.dev, "Trying HCLK/%d...", i); - rc = aspeed_smc_calibrate_reads(chip, i, golden_buf, test_buf); + dev_dbg(chip->nor.dev, "Trying HCLK/%d [%08x] ...", i, tv); + rc = info->calibrate(chip, i, golden_buf, test_buf); if (rc == 0) best_div = i; }