@@ -800,6 +800,12 @@ static int mtdchar_ioctl(struct file *file, u_int cmd, u_long arg)
break;
}
+ case MEMSETDEFAULTLOCKED:
+ {
+ ret = mtd_set_default_locked(mtd);
+ break;
+ }
+
case MEMLOCK:
{
struct erase_info_user einfo;
@@ -1715,6 +1715,14 @@ int mtd_lock_user_prot_reg(struct mtd_info *mtd, loff_t from, size_t len)
}
EXPORT_SYMBOL_GPL(mtd_lock_user_prot_reg);
+int mtd_set_default_locked(struct mtd_info *mtd)
+{
+ if (!mtd->_set_default_locked)
+ return -EOPNOTSUPP;
+ return mtd->_set_default_locked(mtd);
+}
+EXPORT_SYMBOL_GPL(mtd_set_default_locked);
+
/* Chip-supported device locking */
int mtd_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
{
@@ -278,6 +278,10 @@ struct flash_info {
#define NO_CHIP_ERASE BIT(12) /* Chip does not support chip erase */
#define SPI_NOR_SKIP_SFDP BIT(13) /* Skip parsing of SFDP tables */
#define USE_CLSR BIT(14) /* use CLSR command */
+#define SPI_NOR_HAS_BPNV BIT(15) /* Block protection bits can be set
+ * non-volatile, meaning all blocks
+ * are protected by default at reset
+ */
/* Part specific fixup hooks. */
const struct spi_nor_fixups *fixups;
@@ -1319,6 +1323,36 @@ static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
return write_sr_and_check(nor, status_new, mask);
}
+/*
+ * Write status Register and configuration register with 2 bytes
+ * The first byte will be written to the status register, while the
+ * second byte will be written to the configuration register.
+ * Return negative if error occurred.
+ */
+static int write_sr_cr(struct spi_nor *nor, u8 *sr_cr)
+{
+ int ret;
+
+ write_enable(nor);
+
+ ret = nor->write_reg(nor, SPINOR_OP_WRSR, sr_cr, 2);
+ if (ret < 0) {
+ dev_err(nor->dev,
+ "error while writing configuration register\n");
+ return -EINVAL;
+ }
+
+ ret = spi_nor_wait_till_ready(nor);
+ if (ret) {
+ dev_err(nor->dev,
+ "timeout while writing configuration register\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+
/*
* Check if a region of the flash is (completely) locked. See stm_lock() for
* more info.
@@ -1337,6 +1371,35 @@ static int stm_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len)
return stm_is_locked_sr(nor, ofs, len, status);
}
+static int spi_nor_set_default_locked(struct mtd_info *mtd)
+{
+ struct spi_nor *nor = mtd_to_spi_nor(mtd);
+ struct device *dev = nor->dev;
+ u8 sr_cr[2];
+ int ret;
+
+ ret = read_cr(nor);
+ if (ret < 0) {
+ dev_err(dev, "error while reading configuration register\n");
+ return -EINVAL;
+ }
+
+ if (ret & CR_BPNV)
+ return 0;
+
+ sr_cr[1] = ret | CR_BPNV;
+
+ /* Keep the current value of the Status Register. */
+ ret = read_sr(nor);
+ if (ret < 0) {
+ dev_err(dev, "error while reading status register\n");
+ return -EINVAL;
+ }
+ sr_cr[0] = ret;
+
+ return write_sr_cr(nor, sr_cr);
+}
+
static int spi_nor_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
{
struct spi_nor *nor = mtd_to_spi_nor(mtd);
@@ -1382,35 +1445,6 @@ static int spi_nor_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len)
return ret;
}
-/*
- * Write status Register and configuration register with 2 bytes
- * The first byte will be written to the status register, while the
- * second byte will be written to the configuration register.
- * Return negative if error occurred.
- */
-static int write_sr_cr(struct spi_nor *nor, u8 *sr_cr)
-{
- int ret;
-
- write_enable(nor);
-
- ret = nor->write_reg(nor, SPINOR_OP_WRSR, sr_cr, 2);
- if (ret < 0) {
- dev_err(nor->dev,
- "error while writing configuration register\n");
- return -EINVAL;
- }
-
- ret = spi_nor_wait_till_ready(nor);
- if (ret) {
- dev_err(nor->dev,
- "timeout while writing configuration register\n");
- return ret;
- }
-
- return 0;
-}
-
/**
* macronix_quad_enable() - set QE bit in Status Register.
* @nor: pointer to a 'struct spi_nor'
@@ -1880,7 +1914,7 @@ static const struct flash_info spi_nor_ids[] = {
{ "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, USE_CLSR) },
{ "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
- { "s25fl512s", INFO(0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | USE_CLSR) },
+ { "s25fl512s", INFO(0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_HAS_BPNV | USE_CLSR) },
{ "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) },
{ "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) },
{ "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) },
@@ -4055,6 +4089,10 @@ int spi_nor_scan(struct spi_nor *nor, const char *name,
mtd->_is_locked = spi_nor_is_locked;
}
+ if (info->flags & SPI_NOR_HAS_BPNV) {
+ mtd->_set_default_locked = spi_nor_set_default_locked;
+ }
+
/* sst nor chips use AAI word program */
if (info->flags & SST_WRITE)
mtd->_write = sst_write;
@@ -313,6 +313,7 @@ struct mtd_info {
int (*_writev) (struct mtd_info *mtd, const struct kvec *vecs,
unsigned long count, loff_t to, size_t *retlen);
void (*_sync) (struct mtd_info *mtd);
+ int (*_set_default_locked) (struct mtd_info *mtd);
int (*_lock) (struct mtd_info *mtd, loff_t ofs, uint64_t len);
int (*_unlock) (struct mtd_info *mtd, loff_t ofs, uint64_t len);
int (*_is_locked) (struct mtd_info *mtd, loff_t ofs, uint64_t len);
@@ -451,6 +452,7 @@ static inline void mtd_sync(struct mtd_info *mtd)
int mtd_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
int mtd_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
int mtd_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len);
+int mtd_set_default_locked(struct mtd_info *mtd);
int mtd_block_isreserved(struct mtd_info *mtd, loff_t ofs);
int mtd_block_isbad(struct mtd_info *mtd, loff_t ofs);
int mtd_block_markbad(struct mtd_info *mtd, loff_t ofs);
@@ -136,6 +136,7 @@
#define FSR_PT_ERR BIT(1) /* Protection error bit */
/* Configuration Register bits. */
+#define CR_BPNV BIT(3) /* Block protection non-volatile */
#define CR_QUAD_EN_SPAN BIT(1) /* Spansion Quad I/O */
/* Status Register 2 bits. */
@@ -204,6 +204,7 @@ struct otp_info {
* without OOB, e.g., NOR flash.
*/
#define MEMWRITE _IOWR('M', 24, struct mtd_write_req)
+#define MEMSETDEFAULTLOCKED _IO('M', 25)
/*
* Obsolete legacy interface. Keep it in order not to break userspace
Setting the BPNV bit defaults the block protection bits BP0-2 to 1 at reset. This means that all the flash sectors are protected until they are explicity unlocked by the user. Together with protection of the status register via the SRWD bit and the WP# signal, this allows a flash device to be effectively protected from erasure by unauthorized actors. The patch has been tested with a Cypress s25fl512s and works as advertised. The concern that I have with this, though, is that the BPNV bit is "write once": if somebody inadvertently sets this feature on the device, it is irrevocable! Whether or not this actually belongs in the mainline kernel is therefore up for debate... Signed-off-by: Jonas Bonn <jonas@norrbonn.se> CC: Marek Vasut <marek.vasut@gmail.com> CC: David Woodhouse <dwmw2@infradead.org> CC: Brian Norris <computersforpeace@gmail.com> CC: Boris Brezillon <bbrezillon@kernel.org> CC: Richard Weinberger <richard@nod.at> CC: linux-mtd@lists.infradead.org --- drivers/mtd/mtdchar.c | 6 +++ drivers/mtd/mtdcore.c | 8 +++ drivers/mtd/spi-nor/spi-nor.c | 98 ++++++++++++++++++++++++----------- include/linux/mtd/mtd.h | 2 + include/linux/mtd/spi-nor.h | 1 + include/uapi/mtd/mtd-abi.h | 1 + 6 files changed, 86 insertions(+), 30 deletions(-)