| Message ID | 20190123075538.12681-1-frieder.schrempf@kontron.de |
|---|---|
| State | Changes Requested |
| Delegated to: | Ambarus Tudor |
| Headers | show |
| Series | [1/2] mtd: spi-nor: Add support for EN25Q80A | expand |
Hi, Frieder, On 01/23/2019 09:56 AM, Schrempf Frieder wrote: > From: Frieder Schrempf <frieder.schrempf@kontron.de> > > This adds support for the EON EN25Q80A, a 8Mb SPI NOR chip. I would suggest to specify who is using this flash and how did you test it. This way we will not end up with support for flashes that are not actually used. > > Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> > --- > drivers/mtd/spi-nor/spi-nor.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c > index 6e13bbd1aaa5..aa8a04293a25 100644 > --- a/drivers/mtd/spi-nor/spi-nor.c > +++ b/drivers/mtd/spi-nor/spi-nor.c > @@ -1737,6 +1737,8 @@ static const struct flash_info spi_nor_ids[] = { > /* EON -- en25xxx */ > { "en25f32", INFO(0x1c3116, 0, 64 * 1024, 64, SECT_4K) }, > { "en25p32", INFO(0x1c2016, 0, 64 * 1024, 64, 0) }, > + { "en25q80a", INFO(0x1c3014, 0, 64 * 1024, 16, > + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, I'm reading EN25Q80A Rev. H, Issue Date: 2012/10/23 datasheet. I don't see the bfpt table described, so probably it doesn't support it. The flash advertises SPINOR_OP_READ_1_4_4 (0xeb), but not SPINOR_OP_READ_1_1_4 (0x6b). In spi_nor_init_params(), when SPI_NOR_QUAD_READ is set, we assume that SNOR_HWCAPS_READ_1_1_4 is supported, so we will use 0x6b for quad reads. I can't see how the flash works with 0x6b, unless there is a bfpt table that indicates support for 0xebh. If it does support bfpt, set just SECT_4K | SPI_NOR_DUAL_READ, the latter will trigger the bfpt parsing. If you will resubmit, please order the entry in alphabetical order, by name. Cheers, ta
Hi Tudor, On 03.02.19 14:33, Tudor.Ambarus@microchip.com wrote: > Hi, Frieder, > > On 01/23/2019 09:56 AM, Schrempf Frieder wrote: >> From: Frieder Schrempf <frieder.schrempf@kontron.de> >> >> This adds support for the EON EN25Q80A, a 8Mb SPI NOR chip. > > I would suggest to specify who is using this flash and how did you test it. This > way we will not end up with support for flashes that are not actually used. Ok. The flash is used by a board that I plan to upstream. Maybe I should just resubmit this together with the actual board support patches? Likewise for my other patch (MX25V8035F), this is for another board I plan to upstream soon. > >> >> Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> >> --- >> drivers/mtd/spi-nor/spi-nor.c | 2 ++ >> 1 file changed, 2 insertions(+) >> >> diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c >> index 6e13bbd1aaa5..aa8a04293a25 100644 >> --- a/drivers/mtd/spi-nor/spi-nor.c >> +++ b/drivers/mtd/spi-nor/spi-nor.c >> @@ -1737,6 +1737,8 @@ static const struct flash_info spi_nor_ids[] = { >> /* EON -- en25xxx */ >> { "en25f32", INFO(0x1c3116, 0, 64 * 1024, 64, SECT_4K) }, >> { "en25p32", INFO(0x1c2016, 0, 64 * 1024, 64, 0) }, >> + { "en25q80a", INFO(0x1c3014, 0, 64 * 1024, 16, >> + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, > > I'm reading EN25Q80A Rev. H, Issue Date: 2012/10/23 > datasheet. I don't see the bfpt table described, so probably it doesn't support > it. The flash advertises SPINOR_OP_READ_1_4_4 (0xeb), but not > SPINOR_OP_READ_1_1_4 (0x6b). In spi_nor_init_params(), when SPI_NOR_QUAD_READ is > set, we assume that SNOR_HWCAPS_READ_1_1_4 is supported, so we will use 0x6b for > quad reads. I can't see how the flash works with 0x6b, unless there is a bfpt > table that indicates support for 0xebh. > > If it does support bfpt, set just SECT_4K | SPI_NOR_DUAL_READ, the latter will > trigger the bfpt parsing. Thanks for explaining this. I missed the point, that SPI_NOR_QUAD_READ actually requires support for SPINOR_OP_READ_1_1_4. > > If you will resubmit, please order the entry in alphabetical order, by name. Ok. Thanks, Frieder
Hi, Frieder, On 02/07/2019 12:06 PM, Schrempf Frieder wrote: > Hi Tudor, > > On 03.02.19 14:33, Tudor.Ambarus@microchip.com wrote: >> Hi, Frieder, >> >> On 01/23/2019 09:56 AM, Schrempf Frieder wrote: >>> From: Frieder Schrempf <frieder.schrempf@kontron.de> >>> >>> This adds support for the EON EN25Q80A, a 8Mb SPI NOR chip. >> I would suggest to specify who is using this flash and how did you test it. This >> way we will not end up with support for flashes that are not actually used. > Ok. The flash is used by a board that I plan to upstream. Maybe I should > just resubmit this together with the actual board support patches? > > Likewise for my other patch (MX25V8035F), this is for another board I > plan to upstream soon. > Sounds good. Cheers, ta
On Thu, 7 Feb 2019 10:16:05 +0000 <Tudor.Ambarus@microchip.com> wrote: > Hi, Frieder, > > On 02/07/2019 12:06 PM, Schrempf Frieder wrote: > > Hi Tudor, > > > > On 03.02.19 14:33, Tudor.Ambarus@microchip.com wrote: > >> Hi, Frieder, > >> > >> On 01/23/2019 09:56 AM, Schrempf Frieder wrote: > >>> From: Frieder Schrempf <frieder.schrempf@kontron.de> > >>> > >>> This adds support for the EON EN25Q80A, a 8Mb SPI NOR chip. > >> I would suggest to specify who is using this flash and how did you test it. This > >> way we will not end up with support for flashes that are not actually used. > > Ok. The flash is used by a board that I plan to upstream. Maybe I should > > just resubmit this together with the actual board support patches? No need to wait for the board patches, they'll be applied independently anyway. Just mention the board you tested it on in the commit message (even if it's not upstream yet) and we should be good. Thanks, Boris
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index 6e13bbd1aaa5..aa8a04293a25 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -1737,6 +1737,8 @@ static const struct flash_info spi_nor_ids[] = { /* EON -- en25xxx */ { "en25f32", INFO(0x1c3116, 0, 64 * 1024, 64, SECT_4K) }, { "en25p32", INFO(0x1c2016, 0, 64 * 1024, 64, 0) }, + { "en25q80a", INFO(0x1c3014, 0, 64 * 1024, 16, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { "en25q32b", INFO(0x1c3016, 0, 64 * 1024, 64, 0) }, { "en25p64", INFO(0x1c2017, 0, 64 * 1024, 128, 0) }, { "en25q64", INFO(0x1c3017, 0, 64 * 1024, 128, SECT_4K) },