| Message ID | 1443655417-14689-3-git-send-email-vz@mleia.com |
|---|---|
| State | Accepted |
| Commit | 08d3cd5ef0633df84d119e939d8d1b56c6e4a5e7 |
| Headers | show |
diff --git a/drivers/mtd/nand/lpc32xx_slc.c b/drivers/mtd/nand/lpc32xx_slc.c index 9ac0f3b..a9e8a02 100644 --- a/drivers/mtd/nand/lpc32xx_slc.c +++ b/drivers/mtd/nand/lpc32xx_slc.c @@ -95,7 +95,7 @@ * slc_tac register definitions **********************************************************************/ /* Computation of clock cycles on basis of controller and device clock rates */ -#define SLCTAC_CLOCKS(c, n, s) (((1 + (c / n)) & 0xF) << s) +#define SLCTAC_CLOCKS(c, n, s) (min_t(u32, 1 + (c / n), 0xF) << s) /* Clock setting for RDY write sample wait time in 2*n clocks */ #define SLCTAC_WDR(n) (((n) & 0xF) << 28)
In case if quotient of controller clock rate to device clock rate does not fit into 4 bit value, choose the maximum acceptable value 0xF, which stands for 16 clocks. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> --- Changes from v1 to v2: * none, new change drivers/mtd/nand/lpc32xx_slc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)