From patchwork Fri Apr 20 09:13:44 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bastian Hecht X-Patchwork-Id: 153975 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from merlin.infradead.org (merlin.infradead.org [IPv6:2001:4978:20e::2]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 8E7D1B703E for ; Fri, 20 Apr 2012 19:15:23 +1000 (EST) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1SL9v8-0001kE-N3; Fri, 20 Apr 2012 09:14:26 +0000 Received: from mail-wg0-f49.google.com ([74.125.82.49]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1SL9uj-0001Yc-Q7 for linux-mtd@lists.infradead.org; Fri, 20 Apr 2012 09:14:02 +0000 Received: by wgbdr1 with SMTP id dr1so6041816wgb.18 for ; Fri, 20 Apr 2012 02:14:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=jfz3qG7kdDNn3cHJ/KZMGALoaxors21NFX7pt2UUm58=; b=IDb9I/ki+4VYog0EHFiGIQjEXJFIb1nnRUKq4RwDz2MzUa7gkMx8TC6ukDhxrkDVIX /j8duHoy2MQsiC8cS2uU88BHv8EsQYCbxYe63i0OQK2Brlh9uvnD9QOOkt+vJvbyhoeq wWE2Z0LN4YqkuhzqgnozzwipdpjdNnvNWN1G6W5iTi2fHSYtO4oFQCq4kIKHWRn+2QBm Gz9RIgiVpPNs0sH22I7c7klbzaRUU9aWpsJ5DInDiU/k9QyE0+3BOYOgHjqu4RhkhQr7 ZuD6lXe9PxtdDGHjvmE3FMOWKdPigZdA65qMF0zyxuq/I43rKYbuFmg6cEhrPFhQTgr6 F2Lw== Received: by 10.180.91.10 with SMTP id ca10mr6127192wib.17.1334913240200; Fri, 20 Apr 2012 02:14:00 -0700 (PDT) Received: from localhost.localdomain ([176.74.57.22]) by mx.google.com with ESMTPS id e6sm4130586wix.8.2012.04.20.02.13.59 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 20 Apr 2012 02:13:59 -0700 (PDT) From: Bastian Hecht To: linux-mtd@lists.infradead.org, linux-sh@vger.kernel.org Subject: [PATCH 3/9] mtd: sh_flctl: Use different OOB layout Date: Fri, 20 Apr 2012 11:13:44 +0200 Message-Id: <1334913230-23615-4-git-send-email-hechtb@gmail.com> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1334913230-23615-1-git-send-email-hechtb@gmail.com> References: <1334913230-23615-1-git-send-email-hechtb@gmail.com> X-Spam-Note: CRM114 invocation failed X-Spam-Score: -2.7 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [74.125.82.49 listed in list.dnswl.org] 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (hechtb[at]googlemail.com) -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature Cc: Magnus Damm , Laurent Pichart X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-mtd-bounces@lists.infradead.org Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org The flctl hardware has changed and a new OOB layout must be adapted for 2k page size NAND chips when using hardware ECC. The related bit fields ECCPOS[0-2] are gone - the bits are marked as reserved now in the datasheet. As there are no official users of the hardware ECC so far, they are completely removed. Signed-off-by: Bastian Hecht --- drivers/mtd/nand/sh_flctl.c | 20 +++++++++++++------- include/linux/mtd/sh_flctl.h | 4 ---- 2 files changed, 13 insertions(+), 11 deletions(-) diff --git a/drivers/mtd/nand/sh_flctl.c b/drivers/mtd/nand/sh_flctl.c index 3c27921..411d783 100644 --- a/drivers/mtd/nand/sh_flctl.c +++ b/drivers/mtd/nand/sh_flctl.c @@ -44,11 +44,17 @@ static struct nand_ecclayout flctl_4secc_oob_16 = { }; static struct nand_ecclayout flctl_4secc_oob_64 = { - .eccbytes = 10, - .eccpos = {48, 49, 50, 51, 52, 53, 54, 55, 56, 57}, - .oobfree = { - {.offset = 60, - . length = 4} }, + .eccbytes = 4 * 10, + .eccpos = { + 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, + 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, + 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, + 54, 55, 56, 57, 58, 59, 60, 61, 62, 63 }, + .oobfree = { + {.offset = 2, .length = 4}, + {.offset = 16, .length = 6}, + {.offset = 32, .length = 6}, + {.offset = 48, .length = 6} }, }; static uint8_t scan_ff_pattern[] = { 0xff, 0xff }; @@ -62,7 +68,7 @@ static struct nand_bbt_descr flctl_4secc_smallpage = { static struct nand_bbt_descr flctl_4secc_largepage = { .options = NAND_BBT_SCAN2NDPAGE, - .offs = 58, + .offs = 0, .len = 2, .pattern = scan_ff_pattern, }; @@ -831,7 +837,7 @@ static int flctl_chip_init_tail(struct mtd_info *mtd) chip->ecc.mode = NAND_ECC_HW; /* 4 symbols ECC enabled */ - flctl->flcmncr_base |= _4ECCEN | ECCPOS2 | ECCPOS_02; + flctl->flcmncr_base |= _4ECCEN; } else { chip->ecc.mode = NAND_ECC_SOFT; } diff --git a/include/linux/mtd/sh_flctl.h b/include/linux/mtd/sh_flctl.h index 6832a90..91c5b01 100644 --- a/include/linux/mtd/sh_flctl.h +++ b/include/linux/mtd/sh_flctl.h @@ -49,7 +49,6 @@ #define FLERRADR(f) (f->reg + 0x98) /* FLCMNCR control bits */ -#define ECCPOS2 (0x1 << 25) #define _4ECCCNTEN (0x1 << 24) #define _4ECCEN (0x1 << 23) #define _4ECCCORRECT (0x1 << 22) @@ -59,9 +58,6 @@ #define QTSEL_E (0x1 << 17) #define ENDIAN (0x1 << 16) /* 1 = little endian */ #define FCKSEL_E (0x1 << 15) -#define ECCPOS_00 (0x00 << 12) -#define ECCPOS_01 (0x01 << 12) -#define ECCPOS_02 (0x02 << 12) #define ACM_SACCES_MODE (0x01 << 10) #define NANWF_E (0x1 << 9) #define SE_D (0x1 << 8) /* Spare area disable */