From patchwork Tue Jun 16 20:23:17 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sandeep Paulraj X-Patchwork-Id: 28743 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from bombadil.infradead.org (bombadil.infradead.org [18.85.46.34]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by bilbo.ozlabs.org (Postfix) with ESMTPS id CCF2CB71D2 for ; Wed, 17 Jun 2009 06:26:04 +1000 (EST) Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.69 #1 (Red Hat Linux)) id 1MGfCO-0001wk-Hv; Tue, 16 Jun 2009 20:24:05 +0000 Received: from devils.ext.ti.com ([198.47.26.153]) by bombadil.infradead.org with esmtps (Exim 4.69 #1 (Red Hat Linux)) id 1MGfC3-0001dU-FT for linux-mtd@lists.infradead.org; Tue, 16 Jun 2009 20:23:53 +0000 Received: from dlep34.itg.ti.com ([157.170.170.115]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id n5GKNJ1l021671; Tue, 16 Jun 2009 15:23:24 -0500 Received: from legion.dal.design.ti.com (localhost [127.0.0.1]) by dlep34.itg.ti.com (8.13.7/8.13.7) with ESMTP id n5GKNIcb017509; Tue, 16 Jun 2009 15:23:18 -0500 (CDT) Received: from gt5d9d821.telogy.design.ti.com (gt5d9d821.telogy.design.ti.com [158.218.100.23]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id n5GKNH902005; Tue, 16 Jun 2009 15:23:18 -0500 (CDT) Received: from gt5d9d821.telogy.design.ti.com (localhost.localdomain [127.0.0.1]) by gt5d9d821.telogy.design.ti.com (8.13.1/8.13.1) with ESMTP id n5GKNH9d011495; Tue, 16 Jun 2009 16:23:17 -0400 Received: (from a0866907@localhost) by gt5d9d821.telogy.design.ti.com (8.13.1/8.13.1/Submit) id n5GKNH0L011492; Tue, 16 Jun 2009 16:23:17 -0400 From: s-paulraj@ti.com To: davinci-linux-open-source@linux.davincidsp.com, linux-mtd@lists.infradead.org, dwmw2@infradead.org, tglx@linutronix.de, akpm@linux-foundation.org Subject: [PATCH v2 2/3] NAND: Add new ECC mode - ECC_HW_OOB_FIRST Date: Tue, 16 Jun 2009 16:23:17 -0400 Message-Id: <1245183797-11469-1-git-send-email-s-paulraj@ti.com> X-Mailer: git-send-email 1.6.0.4 X-Spam-Score: 0.0 (/) Cc: Sneha Narnakaje , Sandeep Paulraj X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.11 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-mtd-bounces@lists.infradead.org Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org From: Sandeep Paulraj The patch applies to linux-mtd GIT tree This patch adds the new mode NAND_ECC_HW_OOB_FIRST in the nand code to support 4-bit ECC on TI DaVinci devices with large page (up to 4K) NAND chips. This ECC mode is similar to NAND_ECC_HW, with the exception of read_page API that first reads the OOB area, reads the data in chunks, feeds the ECC from OOB area to the ECC hw engine and perform any correction on the data as per the ECC status reported by the engine. "ECC_HW_OOB_FIRST" name suggested by Thomas Gleixner Reviewed-by: David Brownell Signed-off-by: Sneha Narnakaje Signed-off-by: Sandeep Paulraj ecc.size; + int eccbytes = chip->ecc.bytes; + int eccsteps = chip->ecc.steps; + uint8_t *p = buf; + uint8_t *ecc_code = chip->buffers->ecccode; + uint32_t *eccpos = chip->ecc.layout->eccpos; + uint8_t *ecc_calc = chip->buffers->ecccalc; + + /* Read the OOB area first */ + chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); + chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); + chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page); + + for (i = 0; i < chip->ecc.total; i++) + ecc_code[i] = chip->oob_poi[eccpos[i]]; + + for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { + int stat; + + chip->ecc.hwctl(mtd, NAND_ECC_READ); + chip->read_buf(mtd, p, eccsize); + chip->ecc.calculate(mtd, p, &ecc_calc[i]); + + stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL); + if (stat < 0) + mtd->ecc_stats.failed++; + else + mtd->ecc_stats.corrected += stat; + } + return 0; +} + +/** * nand_read_page_syndrome - [REPLACABLE] hardware ecc syndrom based page read * @mtd: mtd info structure * @chip: nand chip info structure @@ -2673,6 +2721,17 @@ int nand_scan_tail(struct mtd_info *mtd) */ switch (chip->ecc.mode) { + case NAND_ECC_HW_OOB_FIRST: + /* Similar to NAND_ECC_HW, but a separate read_page handle */ + if (!chip->ecc.calculate || !chip->ecc.correct || + !chip->ecc.hwctl) { + printk(KERN_WARNING "No ECC functions supplied, " + "Hardware ECC not possible\n"); + BUG(); + } + if (!chip->ecc.read_page) + chip->ecc.read_page = nand_read_page_hwecc_oob_first; + case NAND_ECC_HW: /* Use standard hwecc read page function ? */ if (!chip->ecc.read_page)